agb/agb/crt0.s

79 lines
2.2 KiB
ArmAsm
Raw Normal View History

2021-08-16 07:18:02 +10:00
.include "src/asm_include.s"
2021-03-07 04:58:59 +11:00
.arm
.global __start
__start:
b .Initialise
@ Filled in by gbafix
.fill 188, 1, 0
2021-06-27 07:25:27 +10:00
@ multiboot launch point
b .Initialise_mb
.byte 0 @ boot mode, BIOS overwrites this value
.byte 0 @ slave ID number
.fill 26, 1, 0 @ unused?
.word 0 @ joybus entrypoint
.Initialise_mb:
swi 0x00250000
@ Set interrupt handler
ldr r0, =InterruptHandler
2021-06-27 07:25:27 +10:00
ldr r1, =0x03007FFC
str r0, [r1]
b .CommonInit
2021-06-27 07:25:27 +10:00
2021-03-07 04:58:59 +11:00
.Initialise:
@ Set interrupt handler
2021-07-29 05:50:56 +10:00
ldr r0, =InterruptHandler
2021-03-07 04:58:59 +11:00
ldr r1, =0x03007FFC
str r0, [r1]
2021-04-16 14:23:38 +10:00
@ copies ewram section in rom to ewram in ram
ldr r0, =__ewram_rom_start @ load memory address storing start of data for ewram in rom
ldr r1, =__ewram_data_start @ load memory address storing location of ewram in ram
ldr r2, =__ewram_rom_length_halfwords @ load number of 16 bit values to copy
swi 0x000B0000 @ call interrupt CpuSet.
@ r0: source
@ r1: destination
@ r2: length + size information
@
@ see: https://mgba-emu.github.io/gbatek/#swi-0bh-gbands7nds9dsi7dsi9---cpuset
.CommonInit:
@ set the waitstate control register to the normal value used in manufactured cartridges
ldr r0, =0x04000204 @ address for waitstate control register
ldr r1, =0x4317 @ WS0/ROM=3,1 clks; SRAM=8 clks; WS2/EEPROM: 8,8 clks; prefetch enabled
strh r1, [r0]
@ copies iwram section in rom to iwram in ram
ldr r0, =__iwram_rom_start
ldr r1, =__iwram_data_start
ldr r2, =__iwram_rom_length_halfwords
2021-04-16 14:23:38 +10:00
swi 0x000B0000
2022-03-22 08:52:56 +11:00
@ enable interrupts
ldr r0, =0x04000208
ldr r1, =1
str r1, [r0]
@ put zero in both r0 and r1
@ This corresponds to zero for argc and argv (which would technically be required for a c runtime)
ldr r0, =0
mov r1, r0
2021-03-07 04:58:59 +11:00
@ load main and branch
ldr r2, =main
bx r2
2021-06-27 07:25:27 +10:00
@ loop if we end up here
1:
b 1b
2021-04-13 10:33:05 +10:00
.pool
2021-03-07 04:58:59 +11:00
.include "interrupt_handler.s"
2021-10-30 01:44:43 +11:00
.include "src/sound/mixer/mixer.s"