2021-08-16 07:18:02 +10:00
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.include "src/asm_include.s"
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2021-03-07 04:58:59 +11:00
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.arm
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.global __start
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__start:
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b .Initialise
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@ Filled in by gbafix
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.fill 188, 1, 0
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2021-06-27 07:25:27 +10:00
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@ multiboot launch point
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b .Initialise_mb
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.byte 0 @ boot mode, BIOS overwrites this value
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.byte 0 @ slave ID number
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.fill 26, 1, 0 @ unused?
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.word 0 @ joybus entrypoint
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.Initialise_mb:
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swi 0x00250000
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@ Set interrupt handler
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2021-06-27 11:46:32 +10:00
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ldr r0, =InterruptHandler
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2021-06-27 07:25:27 +10:00
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ldr r1, =0x03007FFC
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str r0, [r1]
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2021-06-27 08:00:10 +10:00
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b .CommonInit
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2021-06-27 07:25:27 +10:00
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2021-03-07 04:58:59 +11:00
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.Initialise:
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@ Set interrupt handler
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2021-07-29 05:50:56 +10:00
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ldr r0, =InterruptHandler
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2021-03-07 04:58:59 +11:00
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ldr r1, =0x03007FFC
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str r0, [r1]
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2021-04-16 14:23:38 +10:00
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@ copies ewram section in rom to ewram in ram
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2021-06-27 08:00:10 +10:00
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ldr r0, =__ewram_rom_start @ load memory address storing start of data for ewram in rom
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ldr r1, =__ewram_data_start @ load memory address storing location of ewram in ram
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ldr r2, =__ewram_rom_length_halfwords @ load number of 16 bit values to copy
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swi 0x000B0000 @ call interrupt CpuSet.
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@ r0: source
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@ r1: destination
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@ r2: length + size information
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@
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@ see: https://mgba-emu.github.io/gbatek/#swi-0bh-gbands7nds9dsi7dsi9---cpuset
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.CommonInit:
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2022-01-04 10:27:31 +11:00
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@ set the waitstate control register to the normal value used in manufactured cartridges
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ldr r0, =0x04000204 @ address for waitstate control register
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ldr r1, =0x4317 @ WS0/ROM=3,1 clks; SRAM=8 clks; WS2/EEPROM: 8,8 clks; prefetch enabled
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strh r1, [r0]
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2021-06-27 08:00:10 +10:00
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@ copies iwram section in rom to iwram in ram
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ldr r0, =__iwram_rom_start
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ldr r1, =__iwram_data_start
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ldr r2, =__iwram_rom_length_halfwords
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2021-04-16 14:23:38 +10:00
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swi 0x000B0000
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2022-03-22 08:52:56 +11:00
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@ enable interrupts
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ldr r0, =0x04000208
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ldr r1, =1
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str r1, [r0]
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2021-05-29 21:18:34 +10:00
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@ put zero in both r0 and r1
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@ This corresponds to zero for argc and argv (which would technically be required for a c runtime)
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ldr r0, =0
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mov r1, r0
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2021-03-07 04:58:59 +11:00
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@ load main and branch
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2021-05-29 21:18:34 +10:00
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ldr r2, =main
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bx r2
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2021-06-27 07:25:27 +10:00
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@ loop if we end up here
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1:
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b 1b
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2021-04-13 10:33:05 +10:00
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.pool
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2021-03-07 04:58:59 +11:00
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2021-06-27 11:46:32 +10:00
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.include "interrupt_handler.s"
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2021-10-30 01:44:43 +11:00
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.include "src/sound/mixer/mixer.s"
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