From 45e9c860dfc9f7d1b45f36bebcd8d8a47f466951 Mon Sep 17 00:00:00 2001
From: Gwilym Kuiper <email@gwilym.dev>
Date: Thu, 15 Sep 2022 21:04:10 +0100
Subject: [PATCH] Fix small issues from latest clippy version

---
 agb/build.rs     | 2 +-
 agb/src/timer.rs | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/agb/build.rs b/agb/build.rs
index 6a08965a..2bb2f4bb 100644
--- a/agb/build.rs
+++ b/agb/build.rs
@@ -36,7 +36,7 @@ fn main() {
             .arg("-mthumb-interwork")
             .arg("-mcpu=arm7tdmi")
             .arg("-g")
-            .args(&["-o", out_file_path.as_str()])
+            .args(["-o", out_file_path.as_str()])
             .arg(a)
             .output()
             .unwrap_or_else(|_| panic!("failed to compile {}", a));
diff --git a/agb/src/timer.rs b/agb/src/timer.rs
index 5797fcdb..6b7c8906 100644
--- a/agb/src/timer.rs
+++ b/agb/src/timer.rs
@@ -79,13 +79,13 @@ impl Timer {
     }
 
     pub fn set_enabled(&mut self, enabled: bool) -> &mut Self {
-        let bit = if enabled { 1 } else { 0 };
+        let bit = u16::from(enabled);
         self.control_register().set_bits(bit, 1, 7);
         self
     }
 
     pub fn set_cascade(&mut self, cascade: bool) -> &mut Self {
-        let bit = if cascade { 1 } else { 0 };
+        let bit = u16::from(cascade);
         self.control_register().set_bits(bit, 1, 2);
         self
     }