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Add collapse test and fix bug uncovered by it
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@ -157,12 +157,12 @@ agb_arm_func agb_rs__mixer_collapse
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push {{r4-r11,lr}}
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push {{r4-r11,lr}}
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CONST_0 .req r7
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CONST_0 .req r7
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CONST_127 .req r8
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CONST_128 .req r8
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TEMP .req r10
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TEMP .req r10
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SWAP_SIGN .req r11
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SWAP_SIGN .req r11
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ldr CONST_0, =0
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ldr CONST_0, =0
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ldr CONST_127, =127
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ldr CONST_128, =128
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ldr SWAP_SIGN, =0x80808080
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ldr SWAP_SIGN, =0x80808080
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mov r4, r2
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mov r4, r2
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@ -192,8 +192,8 @@ SWAP_SIGN .req r11
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.macro load_sample left_reg:req right_reg:req
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.macro load_sample left_reg:req right_reg:req
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mov \right_reg, \left_reg, lsl #16 @ push the sample 16 bits first
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mov \right_reg, \left_reg, lsl #16 @ push the sample 16 bits first
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add \right_reg, CONST_127, \right_reg, asr #20 @ move right sample back to being the correct value
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add \right_reg, CONST_128, \right_reg, asr #20 @ move right sample back to being the correct value
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add \left_reg, CONST_127, \left_reg, asr #20 @ now we only have the left sample
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add \left_reg, CONST_128, \left_reg, asr #20 @ now we only have the left sample
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clamp_s8 \left_reg @ clamp the audio to 8 bit values
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clamp_s8 \left_reg @ clamp the audio to 8 bit values
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clamp_s8 \right_reg
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clamp_s8 \right_reg
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@ -470,3 +470,64 @@ impl MixerBuffer {
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}
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}
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}
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}
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}
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}
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#[cfg(test)]
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mod test {
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use crate::fixnum::num;
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use alloc::vec;
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use super::*;
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#[test_case]
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fn collapse_should_correctly_reduce_size_of_input(_: &mut crate::Gba) {
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let input: &[Num<i16, 4>] = &[
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num!(10.0),
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num!(10.0),
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num!(5.0),
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num!(5.0),
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num!(-10.0),
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num!(-10.5),
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num!(-5.9),
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num!(-5.2),
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num!(0.0),
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num!(1.1),
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num!(2.2),
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num!(3.3),
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num!(155.4),
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num!(-230.5),
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num!(400.6),
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num!(-700.7),
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num!(10.0),
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num!(10.0),
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num!(5.0),
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num!(5.0),
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num!(-10.0),
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num!(-10.5),
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num!(-5.9),
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num!(-5.2),
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num!(0.0),
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num!(1.1),
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num!(2.2),
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num!(3.3),
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num!(155.4),
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num!(-230.5),
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num!(400.6),
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num!(-700.7),
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];
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let mut output_buffer = vec![0i8; input.len()];
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unsafe {
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agb_rs__mixer_collapse(output_buffer.as_mut_ptr(), input.as_ptr(), input.len() / 2);
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}
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// output will be unzipped, so input is LRLRLRLRLRLRLR... and output is LLLLLLRRRRRR
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assert_eq!(
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output_buffer,
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&[
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10, 5, -10, -6, 0, 2, 127, 127, 10, 5, -10, -6, 0, 2, 127, 127, 10, 5, -11, -6, 1,
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3, -128, -128, 10, 5, -11, -6, 1, 3, -128, -128
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]
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);
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}
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}
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