alex/agb
1
0
Fork 0
mirror of https://github.com/italicsjenga/agb.git synced 2025-01-11 09:31:34 +11:00
Code Issues Packages Projects Releases Wiki Activity

remove prints

Browse source
This commit is contained in:
Alex Janka 2023-04-16 09:21:38 +10:00
parent 8e04c415d2
commit 911b60bcd1
1 changed files with 1 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
agb/src/serial_link/mod.rs
View file

@ -2,7 +2,7 @@ use core::ops::{Deref, DerefMut};
use embedded_hal::serial::{Read, Write}; use embedded_hal::serial::{Read, Write};
use crate::{memory_mapped::MemoryMapped, println}; use crate::memory_mapped::MemoryMapped;
const SIODATA8: MemoryMapped<u16> = unsafe { MemoryMapped::new(0x0400_012A) }; const SIODATA8: MemoryMapped<u16> = unsafe { MemoryMapped::new(0x0400_012A) };
const SIOCNT: MemoryMapped<u16> = unsafe { MemoryMapped::new(0x0400_0128) }; const SIOCNT: MemoryMapped<u16> = unsafe { MemoryMapped::new(0x0400_0128) };
@ -17,9 +17,7 @@ pub struct LinkPortUart;
impl LinkPortUart { impl LinkPortUart {
pub fn init(rate: BaudRate, with_interrupts: bool, clear_to_send: bool) -> Self { pub fn init(rate: BaudRate, with_interrupts: bool, clear_to_send: bool) -> Self {
println!("begin init");
RCNT.set(0x0); RCNT.set(0x0);
println!("have set rcnt");
SIOCNT.set(0x0); SIOCNT.set(0x0);
let reg: u16 = SioControlReg::default_uart() let reg: u16 = SioControlReg::default_uart()
.with_baud(rate) .with_baud(rate)
@ -27,7 +25,6 @@ impl LinkPortUart {
.with_cts(clear_to_send) .with_cts(clear_to_send)
.into(); .into();
SIOCNT.set(reg); SIOCNT.set(reg);
println!("have set siocnt to {reg:#X}/{reg:#b}");
Self Self
} }
} }