diff --git a/agb/src/dma.rs b/agb/src/dma.rs
index f57008e8..53de7f04 100644
--- a/agb/src/dma.rs
+++ b/agb/src/dma.rs
@@ -73,9 +73,11 @@ impl Dma {
 
         let n_transfers = (size_of::<T>() / 2) as u32;
 
-        self.source_addr.set(handle.data.as_ptr() as u32);
+        self.source_addr.set(handle.data.as_ptr().add(1) as u32);
         self.dest_addr.set(location.memory_location as u32);
 
+        location.memory_location.write_volatile(values[0]);
+
         self.ctrl_addr.set(
             (0b10 << 0x15) | // keep destination address fixed
             // (0b00 << 0x17) | // increment the source address each time