mirror of
https://github.com/italicsjenga/agb.git
synced 2024-12-23 08:11:33 +11:00
idk what i scrwed up
This commit is contained in:
parent
c7591a3e37
commit
cd50bf9673
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@ -1,16 +1,9 @@
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use self::uart::UartSioControl;
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pub use self::{
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normal::{ClockSource, LinkPortNormal},
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uart::{BaudRate, LinkPortUart},
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};
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use crate::memory_mapped::MemoryMapped;
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use core::ops::{Deref, DerefMut};
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mod normal;
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mod uart;
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use embedded_hal::serial::{Read, Write};
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use crate::{memory_mapped::MemoryMapped, println};
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// const SIODATA32LOW: MemoryMapped<u16> = unsafe { MemoryMapped::new(0x0400_0120) };
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// const SIODATA32HIGH: MemoryMapped<u16> = unsafe { MemoryMapped::new(0x0400_0122) };
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const SIODATA8: MemoryMapped<u16> = unsafe { MemoryMapped::new(0x0400_012A) };
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const SIOCNT: MemoryMapped<u16> = unsafe { MemoryMapped::new(0x0400_0128) };
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const RCNT: MemoryMapped<u16> = unsafe { MemoryMapped::new(0x0400_0134) };
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@ -20,11 +13,76 @@ pub enum LinkPortError {
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GbaErrorBit,
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}
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#[allow(dead_code)]
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enum SioControlReg {
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Normal,
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Multi,
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Uart(UartSioControl),
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pub struct LinkPortUart;
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impl LinkPortUart {
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pub fn init(rate: BaudRate, with_interrupts: bool, clear_to_send: bool) -> Self {
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println!("begin init");
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RCNT.set(0x0);
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println!("have set rcnt");
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SIOCNT.set(0x0);
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let reg: u16 = SioControlReg::default_uart()
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.with_baud(rate)
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.with_interrupts(with_interrupts)
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.with_cts(clear_to_send)
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.into();
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SIOCNT.set(reg);
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println!("have set siocnt to {reg:#X}/{reg:#b}");
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Self
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}
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}
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impl Read<u8> for LinkPortUart {
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type Error = LinkPortError;
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fn read(&mut self) -> Result<u8, nb::Error<LinkPortError>> {
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match SioControlReg::from(SIOCNT.get()) {
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v if *v.error => Err(nb::Error::Other(LinkPortError::GbaErrorBit)),
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v if *v.recv_empty => Err(nb::Error::WouldBlock),
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_ => Ok((SIODATA8.get() & 0xFF) as u8),
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}
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}
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}
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impl Write<u8> for LinkPortUart {
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type Error = LinkPortError;
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fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
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match self.flush() {
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Ok(_) => {
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SIODATA8.set(word as u16);
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Ok(())
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}
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Err(e) => Err(e),
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}
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}
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fn flush(&mut self) -> nb::Result<(), Self::Error> {
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match SioControlReg::from(SIOCNT.get()) {
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v if *v.error => Err(nb::Error::Other(LinkPortError::GbaErrorBit)),
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v if *v.send_full => Err(nb::Error::WouldBlock),
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_ => Ok(()),
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}
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}
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}
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pub enum BaudRate {
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B9600 = 0b00,
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B38400 = 0b01,
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B57600 = 0b10,
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B115200 = 0b11,
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}
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impl From<u16> for BaudRate {
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fn from(value: u16) -> Self {
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match value {
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0b00 => Self::B9600,
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0b01 => Self::B38400,
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0b10 => Self::B57600,
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0b11 => Self::B115200,
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_ => panic!("passed invalid value"),
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}
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}
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}
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pub enum SioMode {
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@ -46,6 +104,96 @@ impl From<u16> for SioMode {
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}
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}
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struct SioControlReg {
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baud_rate: BaudRate, // 0-1
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flow_control: BoolField, // 2
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parity_odd: BoolField, // 3
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send_full: BoolField, // 4
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recv_empty: BoolField, // 5
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error: BoolField, // 6
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data_8bit: BoolField, // 7
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fifo_enabled: BoolField, // 8
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parity_enabled: BoolField, // 9
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tx_enabled: BoolField, // 10
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rx_enabled: BoolField, // 11
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mode: SioMode, // 12-13
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irq_enable: BoolField, // 14
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}
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impl SioControlReg {
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fn default_uart() -> Self {
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Self {
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baud_rate: BaudRate::B9600,
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flow_control: BoolField(false),
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parity_odd: BoolField(false),
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send_full: BoolField(false),
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recv_empty: BoolField(false),
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error: BoolField(false),
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data_8bit: BoolField(true),
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// fifo_enabled: BoolField(true),
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fifo_enabled: BoolField(true),
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parity_enabled: BoolField(false),
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tx_enabled: BoolField(true),
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rx_enabled: BoolField(true),
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mode: SioMode::Uart,
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irq_enable: BoolField(false),
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}
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}
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fn with_baud(mut self, rate: BaudRate) -> Self {
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self.baud_rate = rate;
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self
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}
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fn with_interrupts(mut self, interrupts: bool) -> Self {
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*self.irq_enable = interrupts;
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self
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}
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fn with_cts(mut self, clear_to_send: bool) -> Self {
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*self.flow_control = clear_to_send;
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self
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}
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}
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impl From<SioControlReg> for u16 {
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fn from(value: SioControlReg) -> Self {
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value.baud_rate as u16
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| u16::from(value.flow_control) << 2
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| u16::from(value.parity_odd) << 3
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| u16::from(value.send_full) << 4
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| u16::from(value.recv_empty) << 5
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| u16::from(value.error) << 6
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| u16::from(value.data_8bit) << 7 // bit start
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| u16::from(value.fifo_enabled) << 8
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| u16::from(value.parity_enabled) << 9
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| u16::from(value.tx_enabled) << 10
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| u16::from(value.rx_enabled) << 11
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| (value.mode as u16) << 12
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| u16::from(value.irq_enable) << 14
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}
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}
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impl From<u16> for SioControlReg {
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fn from(value: u16) -> Self {
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Self {
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baud_rate: BaudRate::from(value & 0b11),
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flow_control: (value & (1 << 2)).into(),
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parity_odd: (value & (1 << 3)).into(),
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send_full: (value & (1 << 4)).into(),
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recv_empty: (value & (1 << 5)).into(),
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error: (value & (1 << 6)).into(),
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data_8bit: (value & (1 << 7)).into(),
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fifo_enabled: (value & (1 << 8)).into(),
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parity_enabled: (value & (1 << 9)).into(),
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tx_enabled: (value & (1 << 10)).into(),
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rx_enabled: (value & (1 << 11)).into(),
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mode: ((value & (0b11 << 12)) >> 12).into(),
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irq_enable: (value & (1 << 14)).into(),
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}
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}
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}
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pub struct BoolField(bool);
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impl Deref for BoolField {
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@ -74,7 +222,7 @@ impl From<BoolField> for u16 {
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impl From<u16> for BoolField {
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fn from(value: u16) -> Self {
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Self((value % 2) != 0)
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Self(value != 0)
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}
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}
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@ -1,148 +0,0 @@
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use crate::println;
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use super::{BoolField, RCNT, SIOCNT};
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pub struct LinkPortNormal<const S: TransferLength>;
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impl<const S: TransferLength> LinkPortNormal<S> {
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pub fn init(clock_source: ClockSource) -> Self {
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println!("begin uart init");
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RCNT.set(0x0);
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println!("have set rcnt");
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SIOCNT.set(0x0);
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let reg: u16 = NormalSioControl::default()
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.with_clock_source(clock_source)
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.with_transfer_length(S)
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.into();
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SIOCNT.set(reg);
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println!("have set siocnt to {reg:#X}/{reg:#b}");
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Self
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}
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}
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pub(super) struct NormalSioControl {
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clock_source: ClockSource, // 0
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clock_rate: InternalClock, // 1
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si_state: BoolField, // 2
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so_inactive: BoolField, // 3
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// 4-6 empty
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start_bit: StartBit, // 7
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// 8-11 empty
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transfer_length: TransferLength, // 12
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// 13 must be 0
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irq_enable: BoolField, // 14
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}
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impl NormalSioControl {
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fn with_clock_source(mut self, source: ClockSource) -> Self {
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self.clock_source = source;
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self
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}
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fn with_transfer_length(mut self, length: TransferLength) -> Self {
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self.transfer_length = length;
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self
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}
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}
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impl Default for NormalSioControl {
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fn default() -> Self {
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Self {
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clock_source: ClockSource::Internal,
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clock_rate: InternalClock::Khz256,
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si_state: BoolField(false),
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so_inactive: BoolField(false),
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start_bit: StartBit::Inactive,
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transfer_length: TransferLength::Bits32,
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irq_enable: BoolField(false),
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}
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}
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}
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impl From<NormalSioControl> for u16 {
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fn from(value: NormalSioControl) -> Self {
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value.clock_source as u16
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| (value.clock_rate as u16) << 1
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| u16::from(value.si_state) << 2
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| u16::from(value.so_inactive) << 3
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| (value.start_bit as u16) << 7
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| (value.transfer_length as u16) << 12
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| u16::from(value.irq_enable) << 14
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}
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}
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impl From<u16> for NormalSioControl {
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fn from(value: u16) -> Self {
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Self {
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clock_source: (value & 1).into(),
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clock_rate: (value & (1 << 1)).into(),
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si_state: (value & (1 << 2)).into(),
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so_inactive: (value & (1 << 3)).into(),
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start_bit: (value & (1 << 7)).into(),
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transfer_length: (value & (1 << 12)).into(),
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irq_enable: (value & (1 << 14)).into(),
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}
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}
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}
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pub enum ClockSource {
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External = 0,
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Internal = 1,
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}
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impl From<u16> for ClockSource {
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fn from(value: u16) -> Self {
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match value % 2 {
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0 => ClockSource::External,
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1 => ClockSource::Internal,
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_ => panic!(),
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}
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}
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}
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pub enum InternalClock {
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Khz256 = 0,
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Mhz2 = 1,
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}
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impl From<u16> for InternalClock {
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fn from(value: u16) -> Self {
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match value % 2 {
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0 => InternalClock::Khz256,
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1 => InternalClock::Mhz2,
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_ => panic!(),
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}
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}
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}
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// automatically reset when transfer complete
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pub enum StartBit {
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Inactive = 0,
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Active = 1,
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}
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impl From<u16> for StartBit {
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fn from(value: u16) -> Self {
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match value % 2 {
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0 => StartBit::Inactive,
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1 => StartBit::Active,
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_ => panic!(),
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}
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}
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}
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#[derive(PartialEq, Eq)]
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pub enum TransferLength {
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Bits8 = 0,
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Bits32 = 1,
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}
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impl From<u16> for TransferLength {
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fn from(value: u16) -> Self {
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match value % 2 {
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0 => TransferLength::Bits8,
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1 => TransferLength::Bits32,
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_ => panic!(),
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}
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}
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}
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@ -1,168 +0,0 @@
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use embedded_hal::serial::{Read, Write};
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use crate::println;
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use super::{BoolField, LinkPortError, SioMode, RCNT, SIOCNT, SIODATA8};
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pub struct LinkPortUart;
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impl LinkPortUart {
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pub fn init(rate: BaudRate, with_interrupts: bool, clear_to_send: bool) -> Self {
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println!("begin uart init");
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RCNT.set(0x0);
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println!("have set rcnt");
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SIOCNT.set(0x0);
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let reg: u16 = UartSioControl::default()
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.with_baud(rate)
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.with_interrupts(with_interrupts)
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.with_cts(clear_to_send)
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.into();
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SIOCNT.set(reg);
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println!("have set siocnt to {reg:#X}/{reg:#b}");
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Self
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}
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}
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impl Read<u8> for LinkPortUart {
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type Error = LinkPortError;
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fn read(&mut self) -> Result<u8, nb::Error<LinkPortError>> {
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match UartSioControl::from(SIOCNT.get()) {
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v if *v.error => Err(nb::Error::Other(LinkPortError::GbaErrorBit)),
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v if *v.recv_empty => Err(nb::Error::WouldBlock),
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_ => Ok((SIODATA8.get() & 0xFF) as u8),
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}
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}
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}
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impl Write<u8> for LinkPortUart {
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type Error = LinkPortError;
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fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
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match self.flush() {
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Ok(_) => {
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SIODATA8.set(word as u16);
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Ok(())
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}
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Err(e) => Err(e),
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}
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}
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fn flush(&mut self) -> nb::Result<(), Self::Error> {
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match UartSioControl::from(SIOCNT.get()) {
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v if *v.error => Err(nb::Error::Other(LinkPortError::GbaErrorBit)),
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v if *v.send_full => Err(nb::Error::WouldBlock),
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_ => Ok(()),
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}
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}
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}
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pub(super) struct UartSioControl {
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baud_rate: BaudRate, // 0-1
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flow_control: BoolField, // 2
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parity_odd: BoolField, // 3
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send_full: BoolField, // 4
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recv_empty: BoolField, // 5
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error: BoolField, // 6
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data_8bit: BoolField, // 7
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fifo_enabled: BoolField, // 8
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parity_enabled: BoolField, // 9
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tx_enabled: BoolField, // 10
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rx_enabled: BoolField, // 11
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mode: SioMode, // 12-13
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irq_enable: BoolField, // 14
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}
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impl Default for UartSioControl {
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fn default() -> Self {
|
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Self {
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baud_rate: BaudRate::B9600,
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flow_control: BoolField(false),
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parity_odd: BoolField(false),
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send_full: BoolField(false),
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recv_empty: BoolField(false),
|
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error: BoolField(false),
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data_8bit: BoolField(true),
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fifo_enabled: BoolField(true),
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parity_enabled: BoolField(false),
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tx_enabled: BoolField(true),
|
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rx_enabled: BoolField(true),
|
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mode: SioMode::Uart,
|
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irq_enable: BoolField(false),
|
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}
|
||||
}
|
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}
|
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|
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impl UartSioControl {
|
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fn with_baud(mut self, rate: BaudRate) -> Self {
|
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self.baud_rate = rate;
|
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self
|
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}
|
||||
|
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fn with_interrupts(mut self, interrupts: bool) -> Self {
|
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*self.irq_enable = interrupts;
|
||||
self
|
||||
}
|
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|
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fn with_cts(mut self, clear_to_send: bool) -> Self {
|
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*self.flow_control = clear_to_send;
|
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self
|
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}
|
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}
|
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|
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impl From<UartSioControl> for u16 {
|
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fn from(value: UartSioControl) -> Self {
|
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value.baud_rate as u16
|
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| u16::from(value.flow_control) << 2
|
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| u16::from(value.parity_odd) << 3
|
||||
| u16::from(value.send_full) << 4
|
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| u16::from(value.recv_empty) << 5
|
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| u16::from(value.error) << 6
|
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| u16::from(value.data_8bit) << 7 // bit start
|
||||
| u16::from(value.fifo_enabled) << 8
|
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| u16::from(value.parity_enabled) << 9
|
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| u16::from(value.tx_enabled) << 10
|
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| u16::from(value.rx_enabled) << 11
|
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| (value.mode as u16) << 12
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| u16::from(value.irq_enable) << 14
|
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}
|
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}
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|
||||
impl From<u16> for UartSioControl {
|
||||
fn from(value: u16) -> Self {
|
||||
Self {
|
||||
baud_rate: BaudRate::from(value & 0b11),
|
||||
flow_control: (value & (1 << 2)).into(),
|
||||
parity_odd: (value & (1 << 3)).into(),
|
||||
send_full: (value & (1 << 4)).into(),
|
||||
recv_empty: (value & (1 << 5)).into(),
|
||||
error: (value & (1 << 6)).into(),
|
||||
data_8bit: (value & (1 << 7)).into(),
|
||||
fifo_enabled: (value & (1 << 8)).into(),
|
||||
parity_enabled: (value & (1 << 9)).into(),
|
||||
tx_enabled: (value & (1 << 10)).into(),
|
||||
rx_enabled: (value & (1 << 11)).into(),
|
||||
mode: ((value & (0b11 << 12)) >> 12).into(),
|
||||
irq_enable: (value & (1 << 14)).into(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub enum BaudRate {
|
||||
B9600 = 0b00,
|
||||
B38400 = 0b01,
|
||||
B57600 = 0b10,
|
||||
B115200 = 0b11,
|
||||
}
|
||||
|
||||
impl From<u16> for BaudRate {
|
||||
fn from(value: u16) -> Self {
|
||||
match value {
|
||||
0b00 => Self::B9600,
|
||||
0b01 => Self::B38400,
|
||||
0b10 => Self::B57600,
|
||||
0b11 => Self::B115200,
|
||||
_ => panic!("passed invalid value"),
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue