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Split into regular, multiboot and common

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This commit is contained in:
Gwilym Inzani 2023-10-17 23:14:18 +01:00
parent 243e810150
commit ec6774ca6b
2 changed files with 35 additions and 24 deletions
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2
agb/gba.ld
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@ -21,7 +21,7 @@ SECTIONS {
. = ORIGIN(rom); . = ORIGIN(rom);
.text : { .text : {
KEEP(*(.entrypoint)); *(.entrypoint.regular .entrypoint.common);
*(.text .text*); *(.text .text*);
. = ALIGN(4); . = ALIGN(4);

57
agb/src/entrypoint.s
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@ -1,32 +1,13 @@
.arm .arm
.global __start .section .entrypoint.regular, "ax", %progbits
.section .entrypoint
.align .align
.global __start
__start: __start:
b .Initialise b .Initialise
@ Filled in by gbafix @ Filled in by gbafix
.fill 188, 1, 0 .space 188
@ multiboot launch point
__mb_entry:
b .Initialise_mb
.byte 0 @ boot mode, BIOS overwrites this value
.byte 0 @ slave ID number
.fill 26, 1, 0 @ unused?
.word 0 @ joybus entrypoint
.Initialise_mb:
swi 0x00250000
@ Set interrupt handler
ldr r0, =InterruptHandler
ldr r1, =0x03007FFC
str r0, [r1]
b .CommonInit
.Initialise: .Initialise:
@ Set interrupt handler @ Set interrupt handler
@ -44,8 +25,38 @@ __mb_entry:
@ r2: length + size information @ r2: length + size information
@ @
@ see: https://mgba-emu.github.io/gbatek/#swi-0bh-gbands7nds9dsi7dsi9---cpuset @ see: https://mgba-emu.github.io/gbatek/#swi-0bh-gbands7nds9dsi7dsi9---cpuset
ldr r0, =CommonInit
bx r0
.CommonInit: .arm
.section .entrypoint.multiboot, "ax", %progbits
.align
@ Filled in by gbafix
.space 192
@ multiboot launch point
__mb_entry:
b .Initialise_mb
.byte 0 @ boot mode, BIOS overwrites this value
.byte 0 @ slave ID number
.space 26 @ unused?
.Initialise_mb:
swi 0x00250000
@ Set interrupt handler
ldr r0, =InterruptHandler
ldr r1, =0x03007FFC
str r0, [r1]
ldr r0, =CommonInit
bx r0
.arm
.section .entrypoint.common, "ax", %progbits
.align
.global CommonInit
CommonInit:
@ set the waitstate control register to the normal value used in manufactured cartridges @ set the waitstate control register to the normal value used in manufactured cartridges
ldr r0, =0x04000204 @ address for waitstate control register ldr r0, =0x04000204 @ address for waitstate control register
ldr r1, =0x4317 @ WS0/ROM=3,1 clks; SRAM=8 clks; WS2/EEPROM: 8,8 clks; prefetch enabled ldr r1, =0x4317 @ WS0/ROM=3,1 clks; SRAM=8 clks; WS2/EEPROM: 8,8 clks; prefetch enabled