From ed2e7dec5cb44fb915b6b9c544fffcf20860deaf Mon Sep 17 00:00:00 2001 From: Gwilym Inzani Date: Wed, 6 Sep 2023 08:34:14 +0100 Subject: [PATCH] Let rust do the register allocation --- agb/src/display/tiled/vram_manager.rs | 32 +++++++++++++-------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/agb/src/display/tiled/vram_manager.rs b/agb/src/display/tiled/vram_manager.rs index e133f4e2..d5526d35 100644 --- a/agb/src/display/tiled/vram_manager.rs +++ b/agb/src/display/tiled/vram_manager.rs @@ -388,27 +388,27 @@ impl VRamManager { match tile_format { TileFormat::FourBpp => core::arch::asm!( ".rept 2", - "ldmia r0!, {{r2-r5}}", - "stmia r1!, {{r2-r5}}", + "ldmia {src}!, {{{tmp1},{tmp2},{tmp3},{tmp4}}}", + "stmia {dest}!, {{{tmp1},{tmp2},{tmp3},{tmp4}}}", ".endr", - inout("r0") tile_data_start => _, - inout("r1") target_location => _, - out("r2") _, - out("r3") _, - out("r4") _, - out("r5") _, + src = inout(reg) tile_data_start => _, + dest = inout(reg) target_location => _, + tmp1 = out(reg) _, + tmp2 = out(reg) _, + tmp3 = out(reg) _, + tmp4 = out(reg) _, ), TileFormat::EightBpp => core::arch::asm!( ".rept 4", - "ldmia r0!, {{r2-r5}}", - "stmia r1!, {{r2-r5}}", + "ldmia {src}!, {{{tmp1},{tmp2},{tmp3},{tmp4}}}", + "stmia {dest}!, {{{tmp1},{tmp2},{tmp3},{tmp4}}}", ".endr", - inout("r0") tile_data_start => _, - inout("r1") target_location => _, - out("r2") _, - out("r3") _, - out("r4") _, - out("r5") _, + src = inout(reg) tile_data_start => _, + dest = inout(reg) target_location => _, + tmp1 = out(reg) _, + tmp2 = out(reg) _, + tmp3 = out(reg) _, + tmp4 = out(reg) _, ), } }