diff --git a/agb/Cargo.toml b/agb/Cargo.toml
index 702c252b..38c3da4d 100644
--- a/agb/Cargo.toml
+++ b/agb/Cargo.toml
@@ -35,7 +35,7 @@ once_cell = { version = "1.20.1", default-features = false, features = [
 	"critical-section",
 ] }
 critical-section = { version = "1.1.2", features = ["restore-state-u16"] }
-embedded-hal = "0.2.7"
+embedded-hal-nb = "1.0.0"
 nb = "1.1"
 
 [package.metadata.docs.rs]
diff --git a/agb/src/serial_link/mod.rs b/agb/src/serial_link/mod.rs
index 869470af..560fe0df 100644
--- a/agb/src/serial_link/mod.rs
+++ b/agb/src/serial_link/mod.rs
@@ -1,6 +1,6 @@
 use core::ops::{Deref, DerefMut};
 
-use embedded_hal::serial::{Read, Write};
+use embedded_hal_nb::serial::{Read, Write};
 
 use crate::memory_mapped::MemoryMapped;
 
@@ -13,6 +13,14 @@ pub enum LinkPortError {
     GbaErrorBit,
 }
 
+impl embedded_hal_nb::serial::Error for LinkPortError {
+    fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
+        match self {
+            LinkPortError::GbaErrorBit => embedded_hal_nb::serial::ErrorKind::Other,
+        }
+    }
+}
+
 pub struct LinkPortUart;
 
 impl LinkPortUart {
@@ -29,9 +37,11 @@ impl LinkPortUart {
     }
 }
 
-impl Read<u8> for LinkPortUart {
+impl embedded_hal_nb::serial::ErrorType for LinkPortUart {
     type Error = LinkPortError;
+}
 
+impl Read<u8> for LinkPortUart {
     fn read(&mut self) -> Result<u8, nb::Error<LinkPortError>> {
         match SioControlReg::from(SIOCNT.get()) {
             v if *v.error => Err(nb::Error::Other(LinkPortError::GbaErrorBit)),
@@ -42,8 +52,6 @@ impl Read<u8> for LinkPortUart {
 }
 
 impl Write<u8> for LinkPortUart {
-    type Error = LinkPortError;
-
     fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
         match self.flush() {
             Ok(_) => {