2023-02-06 20:54:26 +11:00
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use std::io::{stdout, Write};
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2023-02-07 09:09:52 +11:00
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use minifb::Key;
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2023-02-06 20:54:26 +11:00
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use crate::verbose_println;
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2023-02-07 09:09:52 +11:00
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use super::{clear_bit, get_bit};
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2023-02-06 20:54:26 +11:00
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pub(crate) type Address = u16;
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pub(crate) type ROM = Vec<u8>;
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2023-02-07 09:09:52 +11:00
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enum JoypadBank {
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Action,
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Direction,
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}
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struct Joypad {
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bank_sel: JoypadBank,
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down: bool,
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up: bool,
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left: bool,
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right: bool,
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start: bool,
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select: bool,
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b: bool,
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a: bool,
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}
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impl Joypad {
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fn as_register(&self) -> u8 {
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let mut reg = 0xFF;
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match self.bank_sel {
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JoypadBank::Action => {
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if self.start {
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reg = clear_bit(reg, 3);
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}
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if self.select {
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reg = clear_bit(reg, 2);
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}
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if self.b {
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reg = clear_bit(reg, 1);
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}
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if self.a {
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reg = clear_bit(reg, 0);
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}
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}
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JoypadBank::Direction => {
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if self.down {
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reg = clear_bit(reg, 3);
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}
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if self.up {
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reg = clear_bit(reg, 2);
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}
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if self.left {
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reg = clear_bit(reg, 1);
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}
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if self.right {
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reg = clear_bit(reg, 0);
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}
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}
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}
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reg
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}
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}
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impl Default for Joypad {
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fn default() -> Self {
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Self {
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bank_sel: JoypadBank::Action,
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down: false,
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up: false,
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left: false,
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right: false,
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start: false,
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select: false,
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b: false,
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a: false,
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}
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}
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}
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2023-02-06 20:54:26 +11:00
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#[allow(dead_code)]
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pub struct Memory {
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pub(super) bootrom: ROM,
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pub(super) bootrom_enabled: bool,
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pub(super) rom: ROM,
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pub(super) vram: [u8; 8192],
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pub(super) ram: [u8; 8192],
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pub(super) switchable_ram: [u8; 8192],
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pub(super) cpu_ram: [u8; 128],
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pub(super) oam: [u8; 160],
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pub(super) interrupts: u8,
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pub(super) ime: bool,
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pub(super) ime_scheduled: u8,
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pub(super) io: [u8; 76],
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pub(super) user_mode: bool,
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2023-02-07 09:09:52 +11:00
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joypad: Joypad,
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2023-02-06 20:54:26 +11:00
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}
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impl Memory {
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pub fn init(bootrom: ROM, bootrom_enabled: bool, rom: ROM) -> Self {
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Self {
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bootrom,
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bootrom_enabled,
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rom,
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vram: [0x0; 8192],
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ram: [0x0; 8192],
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switchable_ram: [0x0; 8192],
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cpu_ram: [0x0; 128],
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oam: [0x0; 160],
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interrupts: 0x0,
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ime: false,
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ime_scheduled: 0x0,
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io: [0xFF; 76],
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user_mode: false,
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2023-02-07 09:09:52 +11:00
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joypad: Joypad::default(),
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2023-02-06 20:54:26 +11:00
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}
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}
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pub fn get(&self, address: Address) -> u8 {
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match address {
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0x0..0x8000 => {
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// rom access
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// todo - switchable rom banks
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if self.bootrom_enabled && ((address as usize) < self.bootrom.len()) {
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return self.bootrom[address as usize];
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} else {
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return self.rom[address as usize];
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}
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}
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0x8000..0xA000 => {
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return self.vram[(address - 0x8000) as usize];
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}
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0xA000..0xC000 => 0xFF,
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0xC000..0xE000 => {
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return self.ram[(address - 0xC000) as usize];
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}
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0xE000..0xFE00 => {
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return self.ram[(address - 0xE000) as usize];
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}
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0xFE00..0xFEA0 => {
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return self.oam[(address - 0xFE00) as usize];
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}
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0xFEA0..0xFF00 => {
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2023-02-07 09:09:52 +11:00
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return 0xFF;
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2023-02-06 20:54:26 +11:00
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}
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2023-02-06 21:00:56 +11:00
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0xFF00..0xFF4C => self.get_io(address),
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2023-02-06 20:54:26 +11:00
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0xFF4C..0xFF80 => {
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// println!("empty space 2 read");
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return 0xFF;
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}
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0xFF80..0xFFFF => {
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return self.cpu_ram[(address - 0xFF80) as usize];
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}
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0xFFFF => {
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return self.interrupts;
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}
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}
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}
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pub fn set(&mut self, address: Address, data: u8) {
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// verbose_println!("write addr: {:#X}, data: {:#X}", address, data);
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match address {
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0x0..0x8000 => {
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// change this with MBC code...
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// println!("tried to write {:#5X} at {:#X}", data, address);
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}
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0x8000..0xA000 => {
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self.vram[(address - 0x8000) as usize] = data;
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}
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0xA000..0xC000 => {
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// panic!("switchable write");
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// self.switchable_ram[(address - 0xA000) as usize] = data;
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}
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0xC000..0xE000 => {
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self.ram[(address - 0xC000) as usize] = data;
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}
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0xE000..0xFE00 => {
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self.ram[(address - 0xE000) as usize] = data;
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}
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0xFE00..0xFEA0 => {
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self.oam[(address - 0xFE00) as usize] = data;
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}
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0xFEA0..0xFF00 => {
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// println!("empty space write: {:#X} to addr {:#X}", data, address);
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}
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2023-02-06 21:00:56 +11:00
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0xFF00..0xFF4C => {
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self.set_io(address, data);
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2023-02-06 20:54:26 +11:00
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// verbose_print!("writing to addr {:#X}\r", address);
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stdout().flush().unwrap();
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}
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0xFF50 => {
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self.bootrom_enabled = false;
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}
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0xFF4C..0xFF50 | 0xFF51..0xFF80 => {
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// println!("empty space 2 write: {:#X} to addr {:#X}", data, address);
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}
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0xFF80..0xFFFF => {
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self.cpu_ram[(address - 0xFF80) as usize] = data;
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}
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0xFFFF => {
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verbose_println!("interrupts set to {:#b}", data);
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verbose_println!(" / {:#X}", data);
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self.interrupts = data;
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}
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}
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}
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2023-02-06 21:00:56 +11:00
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fn get_io(&self, address: Address) -> u8 {
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if address == 0xFF00 {
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2023-02-07 09:09:52 +11:00
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return self.joypad.as_register();
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2023-02-06 21:00:56 +11:00
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}
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return self.io[(address - 0xFF00) as usize];
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}
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fn set_io(&mut self, address: Address, data: u8) {
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let addr_l = (address - 0xFF00) as usize;
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if !self.user_mode {
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self.io[addr_l] = data;
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} else {
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match address {
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0xFF02 => {
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if data == 0x81 {
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print!("{}", self.get(0xFF01) as char);
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stdout().flush().unwrap();
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}
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}
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0xFF04 => self.io[addr_l] = 0,
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2023-02-07 08:38:21 +11:00
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0xFF00 => {
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// joypad
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2023-02-07 09:09:52 +11:00
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if !get_bit(data, 5) {
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self.joypad.bank_sel = JoypadBank::Action
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}
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if !get_bit(data, 4) {
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self.joypad.bank_sel = JoypadBank::Direction
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}
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2023-02-07 08:38:21 +11:00
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}
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0xFF11 | 0xFF14 | 0xFF16 | 0xFF19 | 0xFF1E | 0xFF23 | 0xFF26 => {
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// sound
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}
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0xFF41 => {
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2023-02-06 21:10:13 +11:00
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// mixed read/write addresses...
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// need to fill these out more...
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// just seeing what breaks...
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}
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2023-02-07 08:38:21 +11:00
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0xFF4D | 0xFF56 => {
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// cgb only
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}
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2023-02-06 21:10:13 +11:00
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0xFF44 | 0xFF76 | 0xFF77 => {
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// read-only addresses
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println!("BANNED write: {:#X} to {:#X}", data, address);
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}
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2023-02-06 21:00:56 +11:00
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_ => {
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self.io[addr_l] = data;
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// panic!("passed non-io address to io handler!");
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}
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}
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}
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}
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2023-02-07 09:09:52 +11:00
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pub fn update_pressed_keys(&mut self, keys: Vec<Key>) {
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self.joypad.down = keys.contains(&Key::Down) || keys.contains(&Key::S);
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self.joypad.up = keys.contains(&Key::Up) || keys.contains(&Key::W);
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self.joypad.left = keys.contains(&Key::Left) || keys.contains(&Key::A);
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self.joypad.right = keys.contains(&Key::Right) || keys.contains(&Key::D);
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self.joypad.start = keys.contains(&Key::Equal);
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self.joypad.select = keys.contains(&Key::Minus);
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self.joypad.a = keys.contains(&Key::Apostrophe);
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self.joypad.b = keys.contains(&Key::Semicolon);
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}
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2023-02-06 20:54:26 +11:00
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}
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