2023-02-07 10:08:34 +11:00
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use crate::processor::memory::Address;
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2023-02-12 09:46:47 +11:00
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pub(super) trait Mbc {
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2023-02-07 10:08:34 +11:00
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fn get(&self, address: Address) -> u8;
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2023-02-11 21:43:36 +11:00
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fn get_ram(&self, address: Address) -> u8;
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2023-02-07 10:08:34 +11:00
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fn set(&mut self, address: Address, data: u8);
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2023-02-11 21:43:36 +11:00
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fn set_ram(&mut self, address: Address, data: u8);
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2023-02-12 17:21:24 +11:00
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fn mbc_type(&self) -> String;
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2023-02-07 10:08:34 +11:00
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}
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2023-02-12 09:46:47 +11:00
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pub(super) struct None {
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2023-02-07 10:08:34 +11:00
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pub(super) data: Vec<u8>,
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}
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2023-02-12 09:46:47 +11:00
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impl None {
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pub(super) fn init(data: Vec<u8>) -> Self {
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Self { data }
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}
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}
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2023-02-12 09:46:47 +11:00
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impl Mbc for None {
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2023-02-07 10:08:34 +11:00
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fn get(&self, address: Address) -> u8 {
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self.data[address as usize]
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}
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2023-02-11 21:43:36 +11:00
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fn get_ram(&self, _address: Address) -> u8 {
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0xFF
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}
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fn set_ram(&mut self, _address: Address, _data: u8) {}
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2023-02-12 09:46:47 +11:00
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fn set(&mut self, _address: Address, _data: u8) {}
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2023-02-09 17:32:47 +11:00
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2023-02-12 17:21:24 +11:00
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fn mbc_type(&self) -> String {
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String::from("None")
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}
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2023-02-07 10:08:34 +11:00
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}
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2023-02-07 19:28:06 +11:00
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#[derive(Clone, Copy)]
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enum BankingMode {
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Simple,
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Advanced,
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}
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2023-02-12 09:46:47 +11:00
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pub(super) struct Mbc1 {
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pub(super) data: Vec<u8>,
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rom_len: usize,
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rom_bank: u8,
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ram_enabled: bool,
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ram: Option<Vec<u8>>,
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ram_bank: u8,
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upper_banks: u8,
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bank_mode: BankingMode,
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}
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const KB: usize = 1024;
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const ROM_BANK_SIZE: usize = 16 * KB;
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const RAM_BANK_SIZE: usize = 8 * KB;
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impl Mbc1 {
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pub(super) fn init(
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data: Vec<u8>,
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rom_size: u8,
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ram_size: u8,
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_save_file: Option<Vec<u8>>,
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) -> Self {
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let rom_len = match rom_size {
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0x00 => 2,
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0x01 => 4,
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0x02 => 8,
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0x03 => 16,
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0x04 => 32,
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0x05 => 64,
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0x06 => 128,
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0x07 => 256,
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0x08 => 512,
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0x52 => 72,
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0x53 => 80,
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0x54 => 96,
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_ => panic!("unacceptable rom size"),
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} * ROM_BANK_SIZE;
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// in kb
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let ram = match ram_size {
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0x00 => None,
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0x01 => Some(vec![0; 2 * KB]),
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0x02 => Some(vec![0; 8 * KB]),
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0x03 => Some(vec![0; 32 * KB]),
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0x04 => Some(vec![0; 128 * KB]),
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0x05 => Some(vec![0; 64 * KB]),
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_ => panic!("unacceptable ram size"),
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};
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Self {
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data,
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rom_len,
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rom_bank: 0x1,
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ram_enabled: false,
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ram,
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ram_bank: 0,
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upper_banks: 0,
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bank_mode: BankingMode::Simple,
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}
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}
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2023-02-07 10:08:34 +11:00
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}
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impl Mbc for Mbc1 {
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fn get(&self, address: Address) -> u8 {
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self.data[self.get_rom_addr(address)]
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}
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fn get_ram(&self, address: Address) -> u8 {
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if self.ram_enabled && let Some(ram) = &self.ram {
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let addr = self.get_ram_addr(address)%ram.len();
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return ram[addr];
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}
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0xFF
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}
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fn set_ram(&mut self, address: Address, data: u8) {
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let mut addr = self.get_ram_addr(address);
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if self.ram_enabled && let Some(ram) = &mut self.ram {
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addr %= ram.len();
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ram[addr] = data;
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}
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}
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fn set(&mut self, address: Address, data: u8) {
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match address {
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0x0..0x2000 => {
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// enable/disable ram
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self.ram_enabled = (data & 0x0F) == 0xA;
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}
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0x2000..0x4000 => {
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// rom bank number - lower 5 bits
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let mut set_data = data & 0b00011111;
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if set_data == 0 {
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set_data = 1;
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}
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self.rom_bank = set_data;
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}
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0x4000..0x6000 => {
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// ram bank OR upper bits 5 & 6 of rom bank
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self.upper_banks = data & 0b11;
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}
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0x6000..0x8000 => {
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// mode select
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self.bank_mode = if (data & 0x1) == 0x1 {
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BankingMode::Advanced
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} else {
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BankingMode::Simple
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};
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}
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_ => {}
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}
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}
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2023-02-09 17:32:47 +11:00
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2023-02-12 17:21:24 +11:00
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fn mbc_type(&self) -> String {
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if let Some(ram) = &self.ram {
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format!("{}KB MBC1 with {}KB RAM", self.rom_len / KB, ram.len() / KB)
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} else {
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format!("{}KB MBC1", self.rom_len / KB)
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}
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}
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}
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2023-02-12 09:46:47 +11:00
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impl Mbc1 {
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fn get_rom_addr(&self, address: Address) -> usize {
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(match address {
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0x0..0x4000 => match self.bank_mode {
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BankingMode::Simple => address as usize,
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BankingMode::Advanced => {
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(address as usize) + (self.upper_banks as usize * 512 * KB)
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}
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},
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0x4000..0x8000 => {
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(address - 0x4000) as usize
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+ (ROM_BANK_SIZE * self.rom_bank as usize)
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+ (self.upper_banks as usize * 512 * KB)
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}
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0xA000..0xC000 => panic!("passed ram address to rom address function"),
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_ => panic!("address {address} incompatible with MBC1"),
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} % self.rom_len)
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}
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fn get_ram_addr(&self, address: Address) -> usize {
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match address {
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0x0..0x8000 => panic!("passed rom address to ram address function"),
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0xA000..0xC000 => match self.bank_mode {
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BankingMode::Simple => {
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(address - 0xA000) as usize + (RAM_BANK_SIZE * self.ram_bank as usize)
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}
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BankingMode::Advanced => {
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(address - 0xA000) as usize
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+ (RAM_BANK_SIZE * self.ram_bank as usize)
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+ (self.upper_banks as usize * 16 * KB)
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}
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},
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_ => panic!("address {address} incompatible with MBC1"),
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}
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}
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}
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