mbc3 first pass - no rtc
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parent
0536d19242
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0417f94518
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@ -1,7 +1,7 @@
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use crate::processor::memory::Address;
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use crate::processor::memory::Address;
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use std::str::from_utf8_unchecked;
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use std::str::from_utf8_unchecked;
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use self::mbcs::{Mbc, Mbc1, Mbc5, None};
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use self::mbcs::{Mbc, Mbc1, Mbc3, Mbc5, None};
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mod mbcs;
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mod mbcs;
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@ -32,6 +32,14 @@ impl Rom {
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println!("MBC1 w/battery - battery not implemented!");
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println!("MBC1 w/battery - battery not implemented!");
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Box::new(Mbc1::init(data, rom_size, ram_size, None))
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Box::new(Mbc1::init(data, rom_size, ram_size, None))
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}
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}
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0x0F => panic!("MBC3 + RTC"),
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0x1F => panic!("MBC3 + RTC + RAM"),
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0x11 => Box::new(Mbc3::init(data, rom_size, 0)),
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0x12 => Box::new(Mbc3::init(data, rom_size, ram_size)),
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0x13 => {
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println!("MBC3 w/battery - battery not implemented!");
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Box::new(Mbc3::init(data, rom_size, 0))
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}
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0x19 => Box::new(Mbc5::init(data, rom_size, 0)),
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0x19 => Box::new(Mbc5::init(data, rom_size, 0)),
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0x1A => Box::new(Mbc5::init(data, rom_size, ram_size)),
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0x1A => Box::new(Mbc5::init(data, rom_size, ram_size)),
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0x1B => {
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0x1B => {
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@ -1,9 +1,11 @@
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use crate::processor::memory::Address;
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use crate::processor::memory::Address;
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mod mbc1;
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mod mbc1;
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mod mbc3;
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mod mbc5;
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mod mbc5;
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mod none;
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mod none;
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pub use mbc1::Mbc1;
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pub use mbc1::Mbc1;
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pub use mbc3::Mbc3;
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pub use mbc5::Mbc5;
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pub use mbc5::Mbc5;
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pub use none::None;
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pub use none::None;
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102
src/processor/memory/rom/mbcs/mbc3.rs
Normal file
102
src/processor/memory/rom/mbcs/mbc3.rs
Normal file
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@ -0,0 +1,102 @@
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use crate::processor::memory::Address;
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use super::{ram_size_kb, rom_banks, Mbc, KB, RAM_BANK_SIZE, ROM_BANK_SIZE};
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pub struct Mbc3 {
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data: Vec<u8>,
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rom_bank: u8,
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rom_size: usize,
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ram: Option<Vec<u8>>,
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ram_bank: u8,
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ram_size: usize,
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ram_enabled: bool,
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}
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impl Mbc3 {
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pub fn init(data: Vec<u8>, rom_size: u8, ram_size: u8) -> Self {
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let ram = ram_size_kb(ram_size).map(|s| vec![0; s * KB]);
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Self {
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data,
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rom_bank: 1,
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rom_size: rom_banks(rom_size) * ROM_BANK_SIZE,
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ram,
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ram_bank: 0,
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ram_size: ram_size_kb(ram_size).map_or(1, |s| s * KB),
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ram_enabled: false,
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}
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}
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fn get_rom_addr(&self, address: Address) -> usize {
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(match address {
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0x0..0x4000 => address as usize,
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0x4000..0x8000 => {
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let internal_addr = address as usize - 0x4000;
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internal_addr + (ROM_BANK_SIZE * self.rom_bank as usize)
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}
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_ => panic!("address {address} incompatible with MBC5"),
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} % self.rom_size)
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}
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fn get_ram_addr(&self, address: Address) -> usize {
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((address as usize - 0xA000) + (RAM_BANK_SIZE * self.ram_bank as usize)) % self.ram_size
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}
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}
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impl Mbc for Mbc3 {
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fn get(&self, address: Address) -> u8 {
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self.data[self.get_rom_addr(address)]
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}
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fn get_ram(&self, address: Address) -> u8 {
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if self.ram_enabled && let Some(ram) = &self.ram {
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ram[self.get_ram_addr(address)]
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} else {
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0xFF
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}
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}
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fn set(&mut self, address: Address, data: u8) {
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match address {
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0x0..0x2000 => {
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if data & 0xF == 0xA {
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self.ram_enabled = true;
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}
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}
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0x2000..0x4000 => {
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self.rom_bank = data & 0b01111111;
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if self.rom_bank == 0 {
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self.rom_bank = 1;
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}
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}
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0x4000..0x6000 => match data {
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0x0..=0x03 => self.ram_bank = data,
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0x08..=0x0C => panic!("rtc bank map: {data:#X}"),
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_ => panic!("ram/rtc bank error: tried to map {data:#X}"),
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},
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0x6000..0x8000 => {
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// RTC
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}
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_ => panic!("unsupported addr"),
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}
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}
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fn set_ram(&mut self, address: Address, data: u8) {
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let real_addr = self.get_ram_addr(address);
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if self.ram_enabled && let Some(ram) = &mut self.ram {
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ram[real_addr] = data;
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}
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}
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fn mbc_type(&self) -> String {
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if let Some(ram) = &self.ram {
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format!(
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"{}KB MBC3 with {}KB RAM",
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self.rom_size / KB,
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ram.len() / KB,
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)
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} else {
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format!("{}KB MBC3", self.rom_size / KB)
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}
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}
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}
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