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split processor to module

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This commit is contained in:
Alex Janka 2023-01-16 12:13:53 +11:00
parent 831e880a37
commit 04261acd53
2 changed files with 93 additions and 89 deletions
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94
src/main.rs
View file

@ -1,6 +1,9 @@
#![feature(exclusive_range_pattern)]
mod processor;
use clap::Parser;
use processor::CPU;
use std::{fs, io};
/// Simple program to greet a person
@ -30,7 +33,7 @@ union Register {
as_u16: u16,
}
struct Memory {
pub struct Memory {
rom: ROM,
vram: [u8; 8192],
ram: [u8; 8192],
@ -125,7 +128,7 @@ impl Memory {
}
}
struct State {
pub struct State {
af: Register,
bc: Register,
de: Register,
@ -148,93 +151,6 @@ impl Default for State {
}
}
struct CPU {
memory: Memory,
state: State,
}
impl CPU {
fn exec_next(&mut self) -> u8 {
let opcode = self.next_opcode();
match opcode {
0x0 => {
// noop
}
0x01 => {
self.state.bc = self.ld_immediate_word();
}
0x11 => {
self.state.de = self.ld_immediate_word();
}
0x21 => {
self.state.hl = self.ld_immediate_word();
}
0x2C => {
unsafe {
self.state.hl.as_u8s.right += 1;
};
}
0x3E => {
self.state.af.as_u8s.left = self.ld_immediate_byte();
}
0x4A => {
unsafe {
self.state.bc.as_u8s.right = self.state.de.as_u8s.left;
};
}
0x4B => {
unsafe {
self.state.bc.as_u8s.right = self.state.de.as_u8s.right;
};
}
0x53 => {
unsafe {
self.state.de.as_u8s.left = self.state.de.as_u8s.right;
};
}
0x66 => {
unsafe {
self.state.hl.as_u8s.left = self.memory.get(self.state.hl.as_u16);
};
}
0xC3 => {
self.state.pc = self.ld_immediate_word();
}
0xEA => {
unsafe {
let address = self.ld_immediate_word().as_u16;
self.memory.set(address, self.state.af.as_u8s.left);
};
}
_ => {
panic!("unimplemented opcode: {:#X}", opcode);
}
};
return opcode;
}
fn next_opcode(&mut self) -> u8 {
unsafe {
let opcode = self.memory.get(self.state.pc.as_u16);
self.state.pc.as_u16 += 0x1;
return opcode;
};
}
fn ld_immediate_word(&mut self) -> Register {
Register {
as_u8s: Inner {
left: self.next_opcode(),
right: self.next_opcode(),
},
}
}
fn ld_immediate_byte(&mut self) -> u8 {
self.next_opcode()
}
}
fn main() {
let args = Args::parse();

88
src/processor.rs Normal file
View file

@ -0,0 +1,88 @@
use crate::{Inner, Memory, Register, State};
pub struct CPU {
pub memory: Memory,
pub state: State,
}
impl CPU {
pub fn exec_next(&mut self) -> u8 {
let opcode = self.next_opcode();
match opcode {
0x0 => {
// noop
}
0x01 => {
self.state.bc = self.ld_immediate_word();
}
0x11 => {
self.state.de = self.ld_immediate_word();
}
0x21 => {
self.state.hl = self.ld_immediate_word();
}
0x2C => {
unsafe {
self.state.hl.as_u8s.right += 1;
};
}
0x3E => {
self.state.af.as_u8s.left = self.ld_immediate_byte();
}
0x4A => {
unsafe {
self.state.bc.as_u8s.right = self.state.de.as_u8s.left;
};
}
0x4B => {
unsafe {
self.state.bc.as_u8s.right = self.state.de.as_u8s.right;
};
}
0x53 => {
unsafe {
self.state.de.as_u8s.left = self.state.de.as_u8s.right;
};
}
0x66 => {
unsafe {
self.state.hl.as_u8s.left = self.memory.get(self.state.hl.as_u16);
};
}
0xC3 => {
self.state.pc = self.ld_immediate_word();
}
0xEA => {
unsafe {
let address = self.ld_immediate_word().as_u16;
self.memory.set(address, self.state.af.as_u8s.left);
};
}
_ => {
panic!("unimplemented opcode: {:#X}", opcode);
}
};
return opcode;
}
fn next_opcode(&mut self) -> u8 {
unsafe {
let opcode = self.memory.get(self.state.pc.as_u16);
self.state.pc.as_u16 += 0x1;
return opcode;
};
}
fn ld_immediate_word(&mut self) -> Register {
Register {
as_u8s: Inner {
left: self.next_opcode(),
right: self.next_opcode(),
},
}
}
fn ld_immediate_byte(&mut self) -> u8 {
self.next_opcode()
}
}