initial: memory and cpu state, rom load path

This commit is contained in:
Alex Janka 2023-01-15 19:53:15 +11:00
commit 0c6c79fa3e
4 changed files with 434 additions and 0 deletions

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.gitignore vendored Normal file
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/target
/test-roms

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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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#![feature(exclusive_range_pattern)]
use clap::Parser;
use std::fs;
/// Simple program to greet a person
#[derive(Parser, Debug)]
#[command(author, version, about, long_about = None)]
struct Args {
/// ROM path
#[arg(short, long)]
rom: String,
}
type Register = u16;
type ROM = Vec<u8>;
type Operation = u8;
struct Memory {
rom: ROM,
}
impl Memory {
fn get(&mut self, address: u16) -> u8 {
match address {
0x0..0x8000 => {
// rom access
// todo - switchable rom banks
return self.rom[address as usize];
}
0x8000..0xA000 => {
panic!("vram");
}
0xA000..0xC000 => {
panic!("switchable ram bank");
}
0xC000..0xE000 => {
panic!("ram")
}
0xE000..0xFE00 => {
panic!("ram mirror")
}
0xFE00..0xFEA0 => {
panic!("sprite attrib memory");
}
0xFEA0..0xFF00 => {
panic!("empty")
}
0xFF00..0xFF4C => {
panic!("I/O");
}
0xFF4C..0xFF80 => {
panic!("empty");
}
0xFF80..0xFFFF => {
panic!("internal ram");
}
0xFFFF => {
panic!("interrupt enable register");
}
}
}
}
#[derive(Debug)]
struct State {
af: Register,
bc: Register,
de: Register,
hl: Register,
sp: Register,
pc: Register,
}
impl Default for State {
fn default() -> Self {
Self {
af: 0x01B0,
bc: 0x0013,
de: 0x00D8,
hl: 0x014D,
sp: 0xFFFE,
pc: 0x0100,
}
}
}
fn main() {
let args = Args::parse();
let rom: ROM = fs::read(args.rom).expect("Could not load ROM");
let state = State::default();
loop {
let op = fetch_op(&rom, state.pc);
}
}
fn fetch_op(rom: &ROM, pc: Register) -> Operation {
rom[pc as usize]
}