From 122bfee8df4598a7c13a9ca0ec42b5a3f0d5a64d Mon Sep 17 00:00:00 2001
From: Alex Janka <alex@alexjanka.com>
Date: Tue, 7 Feb 2023 22:49:08 +1100
Subject: [PATCH] implement HALT

---
 src/processor/mod.rs     | 14 +++++++++++---
 src/processor/opcodes.rs |  3 ++-
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/processor/mod.rs b/src/processor/mod.rs
index e3c5773..7201207 100644
--- a/src/processor/mod.rs
+++ b/src/processor/mod.rs
@@ -29,6 +29,7 @@ pub struct CPU {
     pub last_instruction_addr: u16,
     pub window: Window,
     pub gpu: GPU,
+    halted: bool,
 }
 
 // Hz
@@ -45,10 +46,19 @@ impl CPU {
             last_instruction_addr: 0x0,
             window,
             gpu: GPU::default(),
+            halted: false,
         }
     }
 
     pub fn exec_next(&mut self) {
+        let interrupt_cycles = self.handle_interrupts();
+        self.increment_timers(interrupt_cycles);
+
+        if self.halted {
+            self.increment_timers(1);
+            return;
+        }
+
         self.last_instruction_addr = self.reg.pc;
         let opcode = self.next_opcode();
         self.last_instruction = opcode;
@@ -69,9 +79,6 @@ impl CPU {
         let cycles = self.run_opcode(opcode);
         self.memory.user_mode = false;
         self.increment_timers(cycles);
-
-        let interrupt_cycles = self.handle_interrupts();
-        self.increment_timers(interrupt_cycles);
     }
 
     fn increment_timers(&mut self, cycles: u8) {
@@ -149,6 +156,7 @@ impl CPU {
     }
 
     fn service_interrupt(&mut self, addr: u16) {
+        self.halted = false;
         self.push(self.reg.pc);
         self.reg.pc = addr;
         self.memory.ime = false;
diff --git a/src/processor/opcodes.rs b/src/processor/opcodes.rs
index 7d5750a..3d00560 100644
--- a/src/processor/opcodes.rs
+++ b/src/processor/opcodes.rs
@@ -552,7 +552,8 @@ impl CPU {
                 2
             }
             0x76 => {
-                panic!("halt")
+                self.halted = true;
+                1
             }
             0x77 => {
                 self.memory.set(self.reg.hl, self.reg.get_8(Reg8::A));