refactor printing + args
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744f769728
commit
13bd9f0a1c
3 changed files with 113 additions and 46 deletions
136
src/main.rs
136
src/main.rs
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@ -2,16 +2,36 @@
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mod processor;
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use clap::Parser;
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use clap::{ArgGroup, Parser};
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use processor::CPU;
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use std::{
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fs,
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io::{self, stdout, Write},
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sync::RwLock,
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};
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#[macro_export]
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macro_rules! verbose_println {
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($($tts:tt)*) => {
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if crate::is_verbose() {
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println!($($tts)*);
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}
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};
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}
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#[macro_export]
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macro_rules! verbose_print {
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($($tts:tt)*) => {
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if crate::is_verbose() {
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print!($($tts)*);
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}
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};
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}
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/// Simple program to greet a person
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#[derive(Parser, Debug)]
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#[command(author, version, about, long_about = None)]
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#[command(group(ArgGroup::new("prints").args(["verbose","cycle_count"])))]
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struct Args {
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/// ROM path
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#[arg(short, long)]
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@ -25,6 +45,14 @@ struct Args {
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#[arg(long)]
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run_bootrom: bool,
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/// Verbose print
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#[arg(short, long)]
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verbose: bool,
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/// Show cycle count
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#[arg(short, long)]
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cycle_count: bool,
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/// Step emulation by...
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#[arg(long)]
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step_by: Option<usize>,
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@ -130,7 +158,8 @@ impl Memory {
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}
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fn set(&mut self, address: Address, data: u8) {
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println!("write addr: {:#X}, data: {:#X}", address, data);
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verbose_println!("write addr: {:#X}, data: {:#X}", address, data);
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match address {
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0x0..0x100 => {
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if !self.bootrom_enabled {
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@ -162,7 +191,7 @@ impl Memory {
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// println!("empty space write: {:#X} to addr {:#X}", data, address);
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}
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0xFF00..0xFF4C => {
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print!("writing to addr {:#X}\r", address);
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verbose_print!("writing to addr {:#X}\r", address);
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stdout().flush().unwrap();
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if address == 0xFF02 && data == 0x81 {
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@ -178,8 +207,8 @@ impl Memory {
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self.cpu_ram[(address - 0xFF80) as usize] = data;
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}
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0xFFFF => {
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println!("interrupts set to {:#b}", data);
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println!(" / {:#X}", data);
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verbose_println!("interrupts set to {:#b}", data);
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verbose_println!(" / {:#X}", data);
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self.interrupts = data;
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}
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}
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@ -247,9 +276,15 @@ fn swap_rom_endian(rom: &ROM) -> ROM {
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static mut PAUSE_ENABLED: bool = false;
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static mut PAUSE_QUEUED: bool = false;
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// static mut VERBOSE: bool = false;
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static VERBOSE: RwLock<bool> = RwLock::new(false);
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fn main() {
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let args = Args::parse();
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{
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let mut v = VERBOSE.write().unwrap();
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*v = args.verbose;
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}
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let rom: ROM = fs::read(args.rom).expect("Could not load ROM");
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let bootrom: ROM = fs::read(args.bootrom).expect("Could not load BootROM");
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@ -269,15 +304,19 @@ fn main() {
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let mut cycle_num = 0;
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let mut instructions_seen = vec![];
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let mut last_state = cpu.state.clone();
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let mut next_state: State;
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let mut next_state = last_state;
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match args.step_by {
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Some(step_size) => loop {
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for _ in 0..step_size {
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cycle_num += 1;
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cpu.exec_next();
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println!(
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"exec {:#4X} from {:#4X}",
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cpu.last_instruction, cpu.last_instruction_addr
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if args.cycle_count {
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print_cycles(&cycle_num);
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}
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run_cycle(
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&mut cpu,
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&mut next_state,
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&mut last_state,
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&mut instructions_seen,
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);
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}
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print!(
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@ -285,39 +324,55 @@ fn main() {
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cycle_num
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);
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stdout().flush().unwrap();
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pause();
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pause_once();
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},
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None => loop {
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let will_pause;
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unsafe {
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will_pause = PAUSE_QUEUED.clone();
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}
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cycle_num += 1;
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// print_cycles(&cycle_num);
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cpu.exec_next();
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unsafe {
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next_state = cpu.state;
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if !PAUSE_ENABLED {
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if next_state.pc.as_u16 >= 0x100 {
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PAUSE_ENABLED = true;
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}
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}
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last_state = next_state;
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if will_pause {
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pause();
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}
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}
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match instructions_seen.contains(&cpu.last_instruction) {
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true => {}
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false => {
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// println!("new instruction enountered: {:#X}", cpu.last_instruction);
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instructions_seen.push(cpu.last_instruction);
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}
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if args.cycle_count {
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print_cycles(&cycle_num);
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}
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run_cycle(
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&mut cpu,
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&mut next_state,
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&mut last_state,
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&mut instructions_seen,
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);
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},
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}
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}
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fn run_cycle(
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cpu: &mut CPU,
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next_state: &mut State,
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last_state: &mut State,
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instructions_seen: &mut Vec<u8>,
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) {
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let will_pause;
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unsafe {
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will_pause = PAUSE_QUEUED.clone();
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}
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cpu.exec_next();
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unsafe {
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*next_state = cpu.state;
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if !PAUSE_ENABLED {
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if next_state.pc.as_u16 >= 0x100 {
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PAUSE_ENABLED = true;
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}
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}
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*last_state = *next_state;
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if will_pause {
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pause();
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}
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}
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match instructions_seen.contains(&cpu.last_instruction) {
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true => {}
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false => {
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// println!("new instruction enountered: {:#X}", cpu.last_instruction);
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instructions_seen.push(cpu.last_instruction);
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}
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}
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}
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#[allow(dead_code)]
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fn pause() {
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unsafe {
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@ -328,6 +383,10 @@ fn pause() {
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}
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}
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}
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#[allow(dead_code)]
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fn pause_once() {
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io::stdin().read_line(&mut String::new()).unwrap();
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}
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#[allow(dead_code)]
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fn print_cycles(cycles: &i32) {
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@ -342,3 +401,10 @@ fn print_cycles(cycles: &i32) {
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);
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stdout().flush().unwrap();
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}
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fn is_verbose() -> bool {
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match VERBOSE.read() {
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Ok(v) => *v,
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Err(_) => false,
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}
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}
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@ -3,7 +3,7 @@ use std::{
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ops::{BitAnd, BitOr, BitXor},
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};
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use crate::{Inner, Memory, Register, State};
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use crate::{verbose_println, Inner, Memory, Register, State};
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mod opcodes;
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@ -33,9 +33,10 @@ impl CPU {
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unsafe { self.last_instruction_addr = self.state.pc.as_u16 };
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let opcode = self.next_opcode();
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self.last_instruction = opcode;
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println!(
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verbose_println!(
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"exec {:#4X} from pc: {:#X}",
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opcode, self.last_instruction_addr
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opcode,
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self.last_instruction_addr
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);
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self.run_opcode(opcode);
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}
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@ -177,15 +178,15 @@ impl CPU {
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fn set_flag(&mut self, flag: FLAGS) {
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if flag == FLAGS::Z {
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println!("setting z flag");
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verbose_println!("setting z flag");
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}
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unsafe {
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println!(
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verbose_println!(
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"setting flag: currently {0:#b} / {0:#X}",
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self.state.af.as_u8s.right
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);
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self.state.af.as_u8s.right = self.state.af.as_u8s.right.bitor(1 << flag as u8);
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println!(
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verbose_println!(
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" now {0:#b} / {0:#X}",
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self.state.af.as_u8s.right
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);
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@ -1,4 +1,4 @@
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use crate::{Inner, Register};
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use crate::{verbose_println, Inner, Register};
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use std::ops::{BitAnd, BitOr, BitXor};
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use super::{as_signed, res, set, swap_nibbles, CPU, FLAGS};
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@ -84,7 +84,7 @@ impl CPU {
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0x20 => {
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let jump_size = self.ld_immediate_byte();
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if self.get_flag(FLAGS::Z) == 0 {
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println!("z flag is 0... so doing jump...");
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verbose_println!("z flag is 0... so doing jump...");
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unsafe {
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self.state.pc.as_u16 = self
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.state
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@ -94,7 +94,7 @@ impl CPU {
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}
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} else {
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unsafe {
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println!(
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verbose_println!(
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"not jumping! z flag is {0:#b}, flags are {1:#b} / {1:#X}",
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self.get_flag(FLAGS::Z),
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self.state.af.as_u8s.right
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@ -117,7 +117,7 @@ impl CPU {
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},
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0x26 => self.state.hl.as_u8s.left = self.ld_immediate_byte(),
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0x27 => unsafe {
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println!("Running DAA instruction (0x27) that I'm not too sure about...");
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verbose_println!("Running DAA instruction (0x27) that I'm not too sure about...");
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if self.get_flag(FLAGS::N) == 0 {
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if self.get_flag(FLAGS::C) == 1 || self.state.af.as_u8s.left > 0x99 {
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self.state.af.as_u8s.left += 0x60;
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@ -133,7 +133,7 @@ impl CPU {
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self.state.af.as_u8s.left -= 0x6;
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}
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}
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println!(
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verbose_println!(
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" ...this set register a to {:#X}...",
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self.state.af.as_u8s.left
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);
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