From 2bc9d0f665b783a98e718cec39bbb5e408b3bdda Mon Sep 17 00:00:00 2001 From: Alex Janka Date: Mon, 13 Feb 2023 14:16:58 +1100 Subject: [PATCH] prepare for dealing with all registers --- src/processor/memory/mmio/apu.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/processor/memory/mmio/apu.rs b/src/processor/memory/mmio/apu.rs index c9a9319..cf8c4b0 100644 --- a/src/processor/memory/mmio/apu.rs +++ b/src/processor/memory/mmio/apu.rs @@ -80,6 +80,8 @@ impl Apu { v = set_or_clear_bit(v, 3, self.channels.four.enabled); v } + 0xFF15 | 0xFF1F | 0xFF27..0xFF30 => 0xFF, + 0x0..0xFF10 | 0xFF40..0xFFFF | 0xFFFF => panic!("non-apu addr in apu"), _ => self.mem[reg(addr)], } } @@ -94,9 +96,7 @@ impl Apu { self.mem[reg(addr)] = (self.mem[reg(addr)] & 0b10111111) | (data & 0b01000000) } 0xFF26 => self.apu_enable = (1 << 7) == (data & 0b10000000), - 0xFF11..0xFF1A | 0xFF1B | 0xFF1D..0xFF23 | 0xFF24..0xFF40 => { - println!("BANNED write in APU: {data:#X} to {addr:#X}") - } + 0xFF11..0xFF1A | 0xFF1B | 0xFF1D..0xFF23 | 0xFF24..0xFF40 => self.mem[reg(addr)] = data, 0x0..0xFF10 | 0xFF40..0xFFFF | 0xFFFF => panic!("non-apu addr in apu"), } }