diff --git a/src/main.rs b/src/main.rs
index 9318d62..9943e65 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -49,6 +49,7 @@ pub struct Memory {
     switchable_ram: [u8; 8192],
     cpu_ram: [u8; 128],
     oam: [u8; 160],
+    ime: bool,
 }
 
 impl Memory {
@@ -60,6 +61,7 @@ impl Memory {
             switchable_ram: [0x0; 8192],
             cpu_ram: [0x0; 128],
             oam: [0x0; 160],
+            ime: false,
         }
     }
 
@@ -98,7 +100,7 @@ impl Memory {
                 return self.cpu_ram[(address - 0xFF80) as usize];
             }
             0xFFFF => {
-                panic!("interrupt enable register memory read???");
+                return if self.ime { 1 } else { 0 };
             }
         }
     }
@@ -136,9 +138,10 @@ impl Memory {
             0xFF80..0xFFFF => {
                 self.cpu_ram[(address - 0xFF80) as usize] = data;
             }
-            0xFFFF => {
-                panic!("interrupt enable register memory write???");
-            }
+            0xFFFF => match data {
+                0x0 => self.ime = false,
+                _ => panic!("wrote weird number to ime: {:#X}", data),
+            },
         }
     }
 }
@@ -182,7 +185,6 @@ fn main() {
     let mut cpu = CPU {
         memory: Memory::init(run_rom),
         state,
-        ime: false,
     };
     match args.step_by {
         Some(step_size) => loop {
diff --git a/src/processor.rs b/src/processor.rs
index 0d99589..5ee7d20 100644
--- a/src/processor.rs
+++ b/src/processor.rs
@@ -16,7 +16,6 @@ enum FLAGS {
 pub struct CPU {
     pub memory: Memory,
     pub state: State,
-    pub ime: bool,
 }
 
 impl CPU {
@@ -829,7 +828,7 @@ impl CPU {
             }
             0xD9 => {
                 self.state.pc = self.pop_word();
-                self.ime = true;
+                self.memory.ime = true;
             }
             0xDA => {
                 let maybe_next = self.ld_immediate_word();
@@ -939,7 +938,7 @@ impl CPU {
                     self.state.af.as_u8s.left = self.memory.get(address.as_u16);
                 };
             }
-            0xF3 => self.ime = false,
+            0xF3 => self.memory.ime = false,
             0xF4 => undefined(0xF4),
             0xF5 => self.push(self.state.af),
             0xF6 => unsafe {
@@ -959,7 +958,7 @@ impl CPU {
                 let address = self.ld_immediate_word().as_u16;
                 self.state.af.as_u8s.left = self.memory.get(address);
             },
-            0xFB => self.ime = true,
+            0xFB => self.memory.ime = true,
             0xFC => undefined(0xFC),
             0xFD => undefined(0xFD),
             0xFE => unsafe {