set dma addr to last loaded

2023-02-09 12:31:57 +11:00 · 2023-02-09 12:31:57 +11:00 · 3d15a1ef6f
parent a462e2cfd2
commit 3d15a1ef6f
1 changed files with 1 additions and 0 deletions
--- a/src/processor/memory.rs
+++ b/src/processor/memory.rs
@ -260,6 +260,7 @@ impl Memory {
                    if data > 0xDF {
                        panic!("dma transfer out of bounds: {:#X}", data);
                    }
+                    self.io[addr_l] = data;
                    let mut addr: u16 = 0x0;
                    addr.set_high(data);
                    for l in 0x0..0xA0 {