From 465b8454f616412423118826e2d87ad98b91c148 Mon Sep 17 00:00:00 2001 From: Alex Janka Date: Wed, 8 Feb 2023 11:11:39 +1100 Subject: [PATCH] lcd status interrupts --- src/processor/gpu.rs | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/processor/gpu.rs b/src/processor/gpu.rs index 3622d82..ce9bb3e 100644 --- a/src/processor/gpu.rs +++ b/src/processor/gpu.rs @@ -266,7 +266,29 @@ impl CPU { fn set_lcd_status(&mut self) { let mut stat = self.memory.get(0xFF41); - stat = set_or_clear_bit(stat, 2, self.memory.get(0xFF44) == self.memory.get(0xFF45)); + + let lyc_eq_ly_enabled = get_bit(stat, 6); + let mode_2_enabled = get_bit(stat, 5); + let mode_1_vblank_enabled = get_bit(stat, 4); + let mode_0_hblank_enabled = get_bit(stat, 3); + + let lyc_eq_ly = self.memory.get(0xFF44) == self.memory.get(0xFF45); + let mode_2 = self.gpu.mode == DrawMode::Mode2; + let mode_1_vblank = self.gpu.mode == DrawMode::VBlank; + let mode_0_hblank = self.gpu.mode == DrawMode::HBlank; + + let mut irq = self.memory.get(0xFF0F); + if (lyc_eq_ly_enabled && lyc_eq_ly) + || (mode_2_enabled && mode_2) + || (mode_1_vblank_enabled && mode_1_vblank) + || (mode_0_hblank_enabled && mode_0_hblank) + { + irq = set_bit(irq, 1); + + self.memory.set(0xFF0F, irq); + } + + stat = set_or_clear_bit(stat, 2, lyc_eq_ly); stat = set_or_clear_bit( stat, 1,