From 4a63e38b29bafc1e02604f8ae58df7aadcbc2e1e Mon Sep 17 00:00:00 2001
From: Alex Janka <alex@alexjanka.com>
Date: Tue, 25 Apr 2023 18:49:18 +1000
Subject: [PATCH] fixed vram dma registers!!

---
 lib/src/processor/memory/mmio/cgb/vram_dma.rs | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/lib/src/processor/memory/mmio/cgb/vram_dma.rs b/lib/src/processor/memory/mmio/cgb/vram_dma.rs
index 7c9bcab..56a4c37 100644
--- a/lib/src/processor/memory/mmio/cgb/vram_dma.rs
+++ b/lib/src/processor/memory/mmio/cgb/vram_dma.rs
@@ -54,6 +54,11 @@ impl VramDma {
         }
     }
 
+    fn reset_registers(&mut self) {
+        self.source = 0;
+        self.destination = 0x8000;
+    }
+
     pub(crate) fn set_register(&mut self, address: VramDmaAddress, data: u8) {
         match address.inner() {
             0xFF51 => self.source.set_high(data),
@@ -95,6 +100,7 @@ where
                     cgb_peripherals.vram_dma.source += length;
                     cgb_peripherals.vram_dma.destination += length;
                     cgb_peripherals.vram_dma.mode = DmaMode::Waiting;
+                    cgb_peripherals.vram_dma.reset_registers();
                     ((l as usize) + 1) * 8
                 }
                 DmaMode::Hblank(l, ref mut progress) => {
@@ -109,7 +115,8 @@ where
                         cgb_peripherals.vram_dma.destination += length;
                         *progress += 1;
                         if *progress > (l as u16) {
-                            cgb_peripherals.vram_dma.mode = DmaMode::Waiting
+                            cgb_peripherals.vram_dma.mode = DmaMode::Waiting;
+                            cgb_peripherals.vram_dma.reset_registers();
                         }
                         8
                     } else {