diff --git a/src/processor/instructions/primitives.rs b/src/processor/instructions/primitives.rs
index e50cfac..70925d4 100644
--- a/src/processor/instructions/primitives.rs
+++ b/src/processor/instructions/primitives.rs
@@ -1,6 +1,6 @@
 use crate::{
     processor::{Cpu, Direction, Flags, SplitRegister},
-    util::{get_bit, get_rotation_carry, rotate, Nibbles},
+    util::{as_signed, get_bit, get_rotation_carry, rotate, Nibbles},
 };
 use std::ops::{BitAnd, BitOr};
 
@@ -106,18 +106,13 @@ impl Cpu {
         }
     }
 
-    pub(crate) fn sp_add(&mut self, first: u16, second: i8) -> u16 {
-        let (result, carry) = first.overflowing_add_signed(second.into());
+    pub(crate) fn sp_add(&mut self, first: u16, second: u8) -> u16 {
+        self.add_u8s(first.get_low(), second, false);
+
         self.clear_flag(Flags::NSubtract);
         self.clear_flag(Flags::Zero);
-        self.set_or_clear_flag(Flags::Carry, carry);
-        self.set_or_clear_flag(
-            Flags::HalfCarry,
-            (((first & 0xFFF).wrapping_add_signed(<i8 as Into<i16>>::into(second) & 0xFFF))
-                & 0x1000)
-                == 0x1000,
-        );
-        result
+
+        first.wrapping_add_signed(as_signed(second).into())
     }
 
     pub(crate) fn add_u8s(&mut self, first: u8, second: u8, with_carry: bool) -> u8 {
diff --git a/src/processor/opcodes.rs b/src/processor/opcodes.rs
index 2bc00fc..92bf565 100644
--- a/src/processor/opcodes.rs
+++ b/src/processor/opcodes.rs
@@ -1130,7 +1130,7 @@ impl Cpu {
                 4
             }
             0xE8 => {
-                let v = as_signed(self.ld_immediate_byte());
+                let v = self.ld_immediate_byte();
                 self.reg.sp = self.sp_add(self.reg.sp, v);
                 4
             }
@@ -1191,7 +1191,7 @@ impl Cpu {
                 4
             }
             0xF8 => {
-                let v = as_signed(self.ld_immediate_byte());
+                let v = self.ld_immediate_byte();
                 self.reg.hl = self.sp_add(self.reg.sp, v);
                 3
             }