wave channel memory implemented
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e80fd6a73a
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5cfe28a309
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@ -208,6 +208,9 @@ impl Apu {
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0xFF16 => self.channels.two.get_length_timer_and_duty_cycle(),
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0xFF16 => self.channels.two.get_length_timer_and_duty_cycle(),
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0xFF17 => self.channels.two.get_volume_and_envelope(),
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0xFF17 => self.channels.two.get_volume_and_envelope(),
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0xFF19 => self.channels.two.get_control(),
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0xFF19 => self.channels.two.get_control(),
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0xFF1A => self.channels.three.get_dac(),
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0xFF1C => self.channels.three.get_volume(),
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0xFF1E => self.channels.three.get_control(),
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0xFF24 => {
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0xFF24 => {
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// NR50 - Master volume + VIN panning
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// NR50 - Master volume + VIN panning
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let mut v =
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let mut v =
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@ -242,6 +245,8 @@ impl Apu {
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0xFF13 | 0xFF18 | 0xFF1B | 0xFF1D | 0xFF20 => 0xFF,
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0xFF13 | 0xFF18 | 0xFF1B | 0xFF1D | 0xFF20 => 0xFF,
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// not registers
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// not registers
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0xFF15 | 0xFF1F | 0xFF27..0xFF30 => 0xFF,
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0xFF15 | 0xFF1F | 0xFF27..0xFF30 => 0xFF,
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// wave ram
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0xFF30..0xFF40 => 0xFF,
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0x0..0xFF10 | 0xFF40..=0xFFFF => panic!("non-apu addr in apu"),
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0x0..0xFF10 | 0xFF40..=0xFFFF => panic!("non-apu addr in apu"),
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_ => self.mem[reg(addr)],
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_ => self.mem[reg(addr)],
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}
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}
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@ -258,8 +263,11 @@ impl Apu {
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0xFF17 => self.channels.two.update_volume_and_envelope(data),
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0xFF17 => self.channels.two.update_volume_and_envelope(data),
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0xFF18 => self.channels.two.update_wavelength_low(data),
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0xFF18 => self.channels.two.update_wavelength_low(data),
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0xFF19 => self.channels.two.update_wavelength_high_and_control(data),
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0xFF19 => self.channels.two.update_wavelength_high_and_control(data),
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0xFF1A => self.masked_io(reg(addr), data, 0b10000000),
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0xFF1A => self.channels.three.update_dac(data),
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0xFF1C => self.masked_io(reg(addr), data, 0b1100000),
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0xFF1B => self.channels.three.update_length(data),
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0xFF1C => self.channels.three.update_volume(data),
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0xFF1D => self.channels.three.update_wavelength_low(data),
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0xFF1E => self.channels.three.update_wavelength_high_and_control(data),
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0xFF20 => self.masked_io(reg(addr), data, 0b111111),
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0xFF20 => self.masked_io(reg(addr), data, 0b111111),
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0xFF23 => {
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0xFF23 => {
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self.mem[reg(addr)] = (self.mem[reg(addr)] & 0b10111111) | (data & 0b01000000)
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self.mem[reg(addr)] = (self.mem[reg(addr)] & 0b10111111) | (data & 0b01000000)
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@ -281,7 +289,8 @@ impl Apu {
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self.mixer.ch4.left = Volume::from_bool(get_bit(data, 7));
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self.mixer.ch4.left = Volume::from_bool(get_bit(data, 7));
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}
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}
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0xFF26 => self.apu_enable = (1 << 7) == (data & 0b10000000),
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0xFF26 => self.apu_enable = (1 << 7) == (data & 0b10000000),
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0xFF11..0xFF1A | 0xFF1B | 0xFF1D..0xFF23 | 0xFF24..0xFF40 => self.mem[reg(addr)] = data,
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0xFF30..0xFF40 => self.channels.three.update_wave_ram(addr, data),
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0xFF11..0xFF1A | 0xFF1D..0xFF23 | 0xFF24..0xFF30 => self.mem[reg(addr)] = data,
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0x0..0xFF10 | 0xFF40..0xFFFF | 0xFFFF => panic!("non-apu addr in apu"),
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0x0..0xFF10 | 0xFF40..0xFFFF | 0xFFFF => panic!("non-apu addr in apu"),
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}
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}
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}
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}
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@ -1,4 +1,7 @@
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use crate::util::{get_bit, set_or_clear_bit};
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use crate::{
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processor::memory::Address,
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util::{get_bit, set_or_clear_bit},
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};
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#[derive(Clone, Copy, PartialEq)]
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#[derive(Clone, Copy, PartialEq)]
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pub(super) enum EnvelopeMode {
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pub(super) enum EnvelopeMode {
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@ -276,13 +279,105 @@ impl PwmChannel {
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}
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}
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}
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}
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enum ShiftVolumePercent {
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Zero,
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TwentyFive,
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Fifty,
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OneHundred,
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}
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pub(super) struct WaveChannel {
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pub(super) struct WaveChannel {
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pub(super) enabled: bool,
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pub(super) enabled: bool,
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dac_enabled: bool,
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length_enable: bool,
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length_timer: u8,
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volume: ShiftVolumePercent,
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wavelength: u16,
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wave_timer: u16,
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wave_position: usize,
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wave_ram: [u8; 16],
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}
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}
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impl WaveChannel {
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impl WaveChannel {
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pub(super) fn new(enabled: bool) -> Self {
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pub(super) fn new(enabled: bool) -> Self {
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Self { enabled }
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let wavelength = 0x7FF;
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Self {
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enabled,
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dac_enabled: false,
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length_enable: false,
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length_timer: 0xFF,
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volume: ShiftVolumePercent::Zero,
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wavelength,
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wave_timer: (2048 - wavelength) * 4,
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wave_position: 1,
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wave_ram: [0; 16],
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}
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}
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fn trigger(&mut self) {
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self.enabled = true;
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}
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pub(super) fn update_dac(&mut self, data: u8) {
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self.dac_enabled = get_bit(data, 7);
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}
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pub(super) fn get_dac(&self) -> u8 {
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set_or_clear_bit(0xFF, 7, self.dac_enabled)
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}
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pub(super) fn update_length(&mut self, data: u8) {
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self.length_timer = data;
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}
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pub(super) fn update_volume(&mut self, data: u8) {
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self.volume = match (data & 0b1100000) >> 5 {
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0b00 => ShiftVolumePercent::Zero,
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0b01 => ShiftVolumePercent::OneHundred,
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0b10 => ShiftVolumePercent::Fifty,
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0b11 => ShiftVolumePercent::TwentyFive,
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_ => panic!("should be unreachable"),
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}
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}
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pub(super) fn get_volume(&self) -> u8 {
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0b10011111
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& (match self.volume {
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ShiftVolumePercent::Zero => 0b00,
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ShiftVolumePercent::TwentyFive => 0b11,
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ShiftVolumePercent::Fifty => 0b10,
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ShiftVolumePercent::OneHundred => 0b01,
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} << 5)
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}
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pub(super) fn update_wavelength_low(&mut self, data: u8) {
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self.wavelength = (self.wavelength & 0xFF00) | (data as u16);
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self.set_wave_timer();
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}
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pub(super) fn update_wavelength_high_and_control(&mut self, data: u8) {
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self.length_enable = get_bit(data, 6);
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self.wavelength = (self.wavelength & 0xFF) | (((data & 0b111) as u16) << 8);
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self.set_wave_timer();
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if get_bit(data, 7) {
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self.trigger();
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}
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}
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pub(super) fn get_control(&self) -> u8 {
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set_or_clear_bit(0xFF, 6, self.length_enable)
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}
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pub(super) fn update_wave_ram(&mut self, addr: Address, data: u8) {
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let real_addr = (addr - 0xFF30) as usize;
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if real_addr >= self.wave_ram.len() {
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panic!("sent the wrong address to update_wave_ram");
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}
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self.wave_ram[real_addr] = data;
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}
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fn set_wave_timer(&mut self) {
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self.wave_timer = (2048 - self.wavelength) * 4;
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}
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}
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}
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}
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