From 5db1fc4127516d4893b4fdceea23540839017b89 Mon Sep 17 00:00:00 2001
From: Alex Janka <alex@alexjanka.com>
Date: Sat, 11 Mar 2023 08:56:44 +1100
Subject: [PATCH] cleanup

---
 lib/src/processor/memory/rom.rs           |  7 ---
 lib/src/processor/memory/rom/mbcs/mbc1.rs | 74 +++++++++++------------
 lib/src/processor/memory/rom/mbcs/mbc3.rs | 30 ---------
 3 files changed, 36 insertions(+), 75 deletions(-)

diff --git a/lib/src/processor/memory/rom.rs b/lib/src/processor/memory/rom.rs
index ff7b4fa..d494acf 100644
--- a/lib/src/processor/memory/rom.rs
+++ b/lib/src/processor/memory/rom.rs
@@ -35,7 +35,6 @@ impl MaybeBufferedSram {
                     .read(true)
                     .open(path)
                     .unwrap();
-                // writer.read_exact(&mut buf).unwrap();
                 writer.read_to_end(&mut buf).unwrap();
                 Some(writer)
             } else {
@@ -140,12 +139,6 @@ impl Rom {
 
         let _gbc_flag = data[0x143];
 
-        // if _gbc_flag & 0b10000000 == 0 {
-        //     get_cgb_compat_palette(&data);
-        // } else {
-        //     println!("CGB game");
-        // }
-
         let _sgb_flag = data[0x146];
         let rom_size = data[0x148];
         let ram_size = data[0x149];
diff --git a/lib/src/processor/memory/rom/mbcs/mbc1.rs b/lib/src/processor/memory/rom/mbcs/mbc1.rs
index 5ee57a9..010cce7 100644
--- a/lib/src/processor/memory/rom/mbcs/mbc1.rs
+++ b/lib/src/processor/memory/rom/mbcs/mbc1.rs
@@ -52,6 +52,42 @@ impl Mbc1 {
             bank_mode: BankingMode::Simple,
         }
     }
+
+    fn get_rom_addr(&self, address: Address) -> usize {
+        (match address {
+            0x0..0x4000 => match self.bank_mode {
+                BankingMode::Simple => address as usize,
+                BankingMode::Advanced => {
+                    (address as usize) + (self.upper_banks as usize * 512 * KB)
+                }
+            },
+            0x4000..0x8000 => {
+                (address - 0x4000) as usize
+                    + (ROM_BANK_SIZE * self.rom_bank as usize)
+                    + (self.upper_banks as usize * 512 * KB)
+            }
+
+            0xA000..0xC000 => panic!("passed ram address to rom address function"),
+            _ => panic!("address {address} incompatible with MBC1"),
+        } % self.rom_len)
+    }
+
+    fn get_ram_addr(&self, address: Address) -> usize {
+        match address {
+            0x0..0x8000 => panic!("passed rom address to ram address function"),
+            0xA000..0xC000 => match self.bank_mode {
+                BankingMode::Simple => {
+                    (address - 0xA000) as usize + (RAM_BANK_SIZE * self.ram_bank as usize)
+                }
+                BankingMode::Advanced => {
+                    (address - 0xA000) as usize
+                        + (RAM_BANK_SIZE * self.ram_bank as usize)
+                        + (self.upper_banks as usize * 16 * KB)
+                }
+            },
+            _ => panic!("address {address} incompatible with MBC1"),
+        }
+    }
 }
 
 impl Mbc for Mbc1 {
@@ -131,41 +167,3 @@ impl Mbc for Mbc1 {
         })
     }
 }
-
-impl Mbc1 {
-    fn get_rom_addr(&self, address: Address) -> usize {
-        (match address {
-            0x0..0x4000 => match self.bank_mode {
-                BankingMode::Simple => address as usize,
-                BankingMode::Advanced => {
-                    (address as usize) + (self.upper_banks as usize * 512 * KB)
-                }
-            },
-            0x4000..0x8000 => {
-                (address - 0x4000) as usize
-                    + (ROM_BANK_SIZE * self.rom_bank as usize)
-                    + (self.upper_banks as usize * 512 * KB)
-            }
-
-            0xA000..0xC000 => panic!("passed ram address to rom address function"),
-            _ => panic!("address {address} incompatible with MBC1"),
-        } % self.rom_len)
-    }
-
-    fn get_ram_addr(&self, address: Address) -> usize {
-        match address {
-            0x0..0x8000 => panic!("passed rom address to ram address function"),
-            0xA000..0xC000 => match self.bank_mode {
-                BankingMode::Simple => {
-                    (address - 0xA000) as usize + (RAM_BANK_SIZE * self.ram_bank as usize)
-                }
-                BankingMode::Advanced => {
-                    (address - 0xA000) as usize
-                        + (RAM_BANK_SIZE * self.ram_bank as usize)
-                        + (self.upper_banks as usize * 16 * KB)
-                }
-            },
-            _ => panic!("address {address} incompatible with MBC1"),
-        }
-    }
-}
diff --git a/lib/src/processor/memory/rom/mbcs/mbc3.rs b/lib/src/processor/memory/rom/mbcs/mbc3.rs
index 103430d..e5ecbc6 100644
--- a/lib/src/processor/memory/rom/mbcs/mbc3.rs
+++ b/lib/src/processor/memory/rom/mbcs/mbc3.rs
@@ -28,36 +28,6 @@ enum RamBank {
     Rtc(RtcRegister),
 }
 
-trait AsRtcRegister {
-    fn get_rtc_register(&self, register: &RtcRegister, is_halted: bool) -> u8;
-    fn set_rtc_register(&mut self, register: &RtcRegister, data: u8);
-}
-
-// impl AsRtcRegister for DateTime<Local> {
-//     fn get_rtc_register(&self, register: &RtcRegister, is_halted: bool) -> u8 {
-//         match register {
-//             RtcRegister::Seconds => self.second() as u8,
-//             RtcRegister::Minutes => self.minute() as u8,
-//             RtcRegister::Hours => self.hour() as u8,
-//             RtcRegister::DayCounterLsb => 0,
-//             RtcRegister::Misc => set_or_clear_bit(0, 6, is_halted),
-//         }
-//     }
-
-//     fn set_rtc_register(&mut self, register: &RtcRegister, data: u8) {
-//         let maybe = match register {
-//             RtcRegister::Seconds => self.with_second(data as u32),
-//             RtcRegister::Minutes => self.with_minute(data as u32),
-//             RtcRegister::Hours => self.with_hour(data as u32),
-//             RtcRegister::DayCounterLsb => None,
-//             RtcRegister::Misc => None,
-//         };
-//         if let Some(is) = maybe {
-//             self.clone_from(&is);
-//         }
-//     }
-// }
-
 struct Rtc {
     base_time: Instant,
     latched_time: Option<Instant>,