comments and a lil fixing
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f42f58a663
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@ -119,6 +119,7 @@ impl Memory {
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}
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}
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fn get_io(&self, address: Address) -> u8 {
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fn get_io(&self, address: Address) -> u8 {
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// range: 0xFF00 - 0xFF4B inclusive
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match address {
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match address {
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0xFF00 => self.joypad.as_register(),
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0xFF00 => self.joypad.as_register(),
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0xFF10..0xFF40 => self.apu.get_register(address),
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0xFF10..0xFF40 => self.apu.get_register(address),
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@ -127,6 +128,7 @@ impl Memory {
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}
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}
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fn set_io(&mut self, address: Address, data: u8) {
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fn set_io(&mut self, address: Address, data: u8) {
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// range: 0xFF00 - 0xFF4B inclusive
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let addr_l = (address - 0xFF00) as usize;
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let addr_l = (address - 0xFF00) as usize;
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if !self.user_mode {
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if !self.user_mode {
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self.io[addr_l] = data;
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self.io[addr_l] = data;
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@ -150,11 +152,7 @@ impl Memory {
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// mixed read/write
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// mixed read/write
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self.masked_io(addr_l, data, 0b01111000);
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self.masked_io(addr_l, data, 0b01111000);
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}
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}
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0xFF4D | 0xFF56 => {
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0xFF03 | 0xFF08..0xFF0F | 0xFF44 => {
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// cgb only
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self.io[addr_l] = data;
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}
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0xFF03 | 0xFF08..0xFF0F | 0xFF44 | 0xFF76 | 0xFF77 => {
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// read-only addresses
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// read-only addresses
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println!("BANNED write: {data:#X} to {address:#X}");
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println!("BANNED write: {data:#X} to {address:#X}");
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}
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}
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@ -170,9 +168,8 @@ impl Memory {
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self.oam[l as usize] = self.get(addr);
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self.oam[l as usize] = self.get(addr);
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}
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}
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}
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}
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_ => {
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0x0..0xFF00 | 0xFF4C..=u16::MAX => panic!("passed wrong address to set_io"),
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self.io[addr_l] = data;
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_ => self.io[addr_l] = data,
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}
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}
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}
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}
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}
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}
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}
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@ -117,7 +117,7 @@ impl Apu {
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0xFF13 | 0xFF18 | 0xFF1B | 0xFF1D | 0xFF20 => 0xFF,
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0xFF13 | 0xFF18 | 0xFF1B | 0xFF1D | 0xFF20 => 0xFF,
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// not registers
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// not registers
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0xFF15 | 0xFF1F | 0xFF27..0xFF30 => 0xFF,
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0xFF15 | 0xFF1F | 0xFF27..0xFF30 => 0xFF,
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0x0..0xFF10 | 0xFF40..0xFFFF | 0xFFFF => panic!("non-apu addr in apu"),
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0x0..0xFF10 | 0xFF40..=0xFFFF => panic!("non-apu addr in apu"),
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_ => self.mem[reg(addr)],
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_ => self.mem[reg(addr)],
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}
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}
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}
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}
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