comments and a lil fixing

This commit is contained in:
Alex Janka 2023-02-15 08:25:04 +11:00
parent f42f58a663
commit 75a9396b57
2 changed files with 6 additions and 9 deletions

View file

@ -119,6 +119,7 @@ impl Memory {
} }
fn get_io(&self, address: Address) -> u8 { fn get_io(&self, address: Address) -> u8 {
// range: 0xFF00 - 0xFF4B inclusive
match address { match address {
0xFF00 => self.joypad.as_register(), 0xFF00 => self.joypad.as_register(),
0xFF10..0xFF40 => self.apu.get_register(address), 0xFF10..0xFF40 => self.apu.get_register(address),
@ -127,6 +128,7 @@ impl Memory {
} }
fn set_io(&mut self, address: Address, data: u8) { fn set_io(&mut self, address: Address, data: u8) {
// range: 0xFF00 - 0xFF4B inclusive
let addr_l = (address - 0xFF00) as usize; let addr_l = (address - 0xFF00) as usize;
if !self.user_mode { if !self.user_mode {
self.io[addr_l] = data; self.io[addr_l] = data;
@ -150,11 +152,7 @@ impl Memory {
// mixed read/write // mixed read/write
self.masked_io(addr_l, data, 0b01111000); self.masked_io(addr_l, data, 0b01111000);
} }
0xFF4D | 0xFF56 => { 0xFF03 | 0xFF08..0xFF0F | 0xFF44 => {
// cgb only
self.io[addr_l] = data;
}
0xFF03 | 0xFF08..0xFF0F | 0xFF44 | 0xFF76 | 0xFF77 => {
// read-only addresses // read-only addresses
println!("BANNED write: {data:#X} to {address:#X}"); println!("BANNED write: {data:#X} to {address:#X}");
} }
@ -170,9 +168,8 @@ impl Memory {
self.oam[l as usize] = self.get(addr); self.oam[l as usize] = self.get(addr);
} }
} }
_ => { 0x0..0xFF00 | 0xFF4C..=u16::MAX => panic!("passed wrong address to set_io"),
self.io[addr_l] = data; _ => self.io[addr_l] = data,
}
} }
} }
} }

View file

@ -117,7 +117,7 @@ impl Apu {
0xFF13 | 0xFF18 | 0xFF1B | 0xFF1D | 0xFF20 => 0xFF, 0xFF13 | 0xFF18 | 0xFF1B | 0xFF1D | 0xFF20 => 0xFF,
// not registers // not registers
0xFF15 | 0xFF1F | 0xFF27..0xFF30 => 0xFF, 0xFF15 | 0xFF1F | 0xFF27..0xFF30 => 0xFF,
0x0..0xFF10 | 0xFF40..0xFFFF | 0xFFFF => panic!("non-apu addr in apu"), 0x0..0xFF10 | 0xFF40..=0xFFFF => panic!("non-apu addr in apu"),
_ => self.mem[reg(addr)], _ => self.mem[reg(addr)],
} }
} }