diff --git a/src/main.rs b/src/main.rs
index 495a58a..52c150a 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -21,8 +21,8 @@ type ROM = Vec<u8>;
 
 #[derive(Clone, Copy)]
 struct Inner {
-    left: u8,
     right: u8,
+    left: u8,
 }
 
 union Register {
@@ -44,6 +44,7 @@ impl Memory {
             ram: [0x0; 8192],
         }
     }
+
     fn get(&self, address: Address) -> u8 {
         match address {
             0x0..0x8000 => {
@@ -83,6 +84,45 @@ impl Memory {
             }
         }
     }
+
+    fn set(&mut self, address: Address, data: u8) {
+        match address {
+            0x0..0x8000 => {
+                panic!("tried to write to rom?");
+                // self.rom[address as usize] = data;
+            }
+            0x8000..0xA000 => {
+                self.vram[(address - 0x8000) as usize] = data;
+            }
+            0xA000..0xC000 => {
+                panic!("switchable ram bank");
+            }
+            0xC000..0xE000 => {
+                self.ram[(address - 0xC000) as usize] = data;
+            }
+            0xE000..0xFE00 => {
+                self.ram[(address - 0xE000) as usize] = data;
+            }
+            0xFE00..0xFEA0 => {
+                panic!("sprite attrib memory");
+            }
+            0xFEA0..0xFF00 => {
+                panic!("empty")
+            }
+            0xFF00..0xFF4C => {
+                panic!("I/O");
+            }
+            0xFF4C..0xFF80 => {
+                panic!("empty");
+            }
+            0xFF80..0xFFFF => {
+                panic!("internal ram");
+            }
+            0xFFFF => {
+                panic!("interrupt enable register");
+            }
+        }
+    }
 }
 
 struct State {
@@ -134,6 +174,24 @@ impl CPU {
                     self.state.hl.as_u8s.right += 1;
                 };
             }
+            0x3E => {
+                self.state.af.as_u8s.left = self.ld_immediate_byte();
+            }
+            0x4A => {
+                unsafe {
+                    self.state.bc.as_u8s.right = self.state.de.as_u8s.left;
+                };
+            }
+            0x4B => {
+                unsafe {
+                    self.state.bc.as_u8s.right = self.state.de.as_u8s.right;
+                };
+            }
+            0x53 => {
+                unsafe {
+                    self.state.de.as_u8s.left = self.state.de.as_u8s.right;
+                };
+            }
             0x66 => {
                 unsafe {
                     self.state.hl.as_u8s.left = self.memory.get(self.state.hl.as_u16);
@@ -142,6 +200,12 @@ impl CPU {
             0xC3 => {
                 self.state.pc = self.ld_immediate_word();
             }
+            0xEA => {
+                unsafe {
+                    let address = self.ld_immediate_word().as_u16;
+                    self.memory.set(address, self.state.af.as_u8s.left);
+                };
+            }
             _ => {
                 panic!("unimplemented opcode: {:#X}", opcode);
             }
@@ -165,6 +229,10 @@ impl CPU {
             },
         }
     }
+
+    fn ld_immediate_byte(&mut self) -> u8 {
+        self.next_opcode()
+    }
 }
 
 fn main() {