more opcodes & opcode refactoring
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parent
04261acd53
commit
90a1c92a0c
2 changed files with 75 additions and 8 deletions
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@ -28,6 +28,7 @@ struct Inner {
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left: u8,
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}
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#[derive(Clone, Copy)]
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union Register {
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as_u8s: Inner,
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as_u16: u16,
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@ -1,5 +1,12 @@
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use crate::{Inner, Memory, Register, State};
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enum FLAGS {
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Z = 7,
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N = 6,
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H = 5,
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C = 4,
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}
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pub struct CPU {
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pub memory: Memory,
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pub state: State,
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@ -12,15 +19,61 @@ impl CPU {
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0x0 => {
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// noop
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}
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0x01 => {
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self.state.bc = self.ld_immediate_word();
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}
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0x11 => {
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self.state.de = self.ld_immediate_word();
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}
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0x21 => {
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self.state.hl = self.ld_immediate_word();
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0x01 => self.state.bc = self.ld_immediate_word(),
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0x02 => unsafe {
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let address = self.state.bc.as_u16;
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self.memory.set(address, self.state.af.as_u8s.left);
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},
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0x03 => unsafe { self.state.bc.as_u16 += 1 },
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0x04 => unsafe { self.state.bc.as_u8s.left += 1 },
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0x05 => unsafe { self.state.bc.as_u8s.left -= 1 },
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0x06 => self.state.bc.as_u8s.left = self.ld_immediate_byte(),
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0x07 => panic!("RCLA instruction: 0x07"),
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0x08 => unsafe {
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let address = self.ld_immediate_word().as_u16;
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let word = self.state.sp;
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self.store_word(address, word);
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},
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0x09 => unsafe { self.state.hl.as_u16 += self.state.bc.as_u16 },
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0x0A => unsafe { self.state.af.as_u8s.left = self.memory.get(self.state.bc.as_u16) },
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0x0B => unsafe { self.state.bc.as_u16 -= 0x1 },
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0x0C => unsafe { self.state.bc.as_u8s.right += 0x1 },
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0x0D => unsafe { self.state.bc.as_u8s.right -= 0x1 },
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0x0E => self.state.bc.as_u8s.right = self.ld_immediate_byte(),
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0x0F => panic!("RRCA instruction: 0x0F"),
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0x10 => panic!("STOP instruction"),
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0x11 => self.state.de = self.ld_immediate_word(),
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0x12 => unsafe {
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let address = self.state.de.as_u16;
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let data = self.state.af.as_u8s.left;
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self.memory.set(address, data);
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},
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0x13 => unsafe { self.state.de.as_u16 -= 0x1 },
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0x14 => unsafe { self.state.de.as_u8s.left += 0x1 },
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0x15 => unsafe { self.state.de.as_u8s.left -= 0x1 },
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0x16 => self.state.de.as_u8s.left = self.ld_immediate_byte(),
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0x17 => panic!("RLA instruction: 0x17"),
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0x18 => unsafe { self.state.pc.as_u16 += self.ld_immediate_byte() as u16 },
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0x19 => unsafe { self.state.hl.as_u16 += self.state.de.as_u16 },
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0x1A => unsafe { self.state.af.as_u8s.left = self.memory.get(self.state.de.as_u16) },
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0x1B => unsafe { self.state.de.as_u16 -= 1 },
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0x1C => unsafe { self.state.de.as_u8s.right += 1 },
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0x1D => unsafe { self.state.de.as_u8s.right -= 1 },
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0x1E => self.state.de.as_u8s.right = self.ld_immediate_byte(),
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0x1F => panic!("RRA instruction: 0x1F"),
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0x20 => {
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let jump_size = self.ld_immediate_byte();
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if self.get_flag(FLAGS::Z) == 0 {
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unsafe { self.state.pc.as_u16 += jump_size as u16 }
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}
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}
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0x21 => self.state.hl = self.ld_immediate_word(),
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0x22 => unsafe {
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self.memory
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.set(self.state.hl.as_u16, self.state.af.as_u8s.left);
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self.state.hl.as_u16 += 1;
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},
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0x23 => unsafe { self.state.hl.as_u16 += 1 },
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0x2C => {
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unsafe {
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self.state.hl.as_u8s.right += 1;
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@ -73,6 +126,13 @@ impl CPU {
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};
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}
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fn store_word(&mut self, address: u16, word: Register) {
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unsafe {
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self.memory.set(address, word.as_u8s.left);
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self.memory.set(address + 1, word.as_u8s.right);
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};
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}
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fn ld_immediate_word(&mut self) -> Register {
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Register {
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as_u8s: Inner {
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@ -85,4 +145,10 @@ impl CPU {
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fn ld_immediate_byte(&mut self) -> u8 {
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self.next_opcode()
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}
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fn get_flag(&mut self, flag: FLAGS) -> u8 {
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unsafe {
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return self.state.af.as_u8s.right & (1 << flag as u8);
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}
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}
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}
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