diff --git a/src/main.rs b/src/main.rs
index 31955ce..93cd6b0 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -11,7 +11,7 @@ use std::{
     sync::RwLock,
 };
 
-use crate::processor::{gpu::GPU, Registers};
+use crate::processor::Registers;
 
 #[macro_export]
 macro_rules! verbose_println {
@@ -68,7 +68,6 @@ type ROM = Vec<u8>;
 pub struct Memory {
     bootrom: ROM,
     bootrom_enabled: bool,
-    interrupt_table: [u8; 256],
     rom: ROM,
     vram: [u8; 8192],
     ram: [u8; 8192],
@@ -86,7 +85,6 @@ impl Memory {
         Self {
             bootrom,
             bootrom_enabled,
-            interrupt_table: [0xFF; 256],
             rom,
             vram: [0x0; 8192],
             ram: [0x0; 8192],
@@ -102,14 +100,7 @@ impl Memory {
 
     fn get(&self, address: Address) -> u8 {
         match address {
-            0x0..0x100 => {
-                if self.bootrom_enabled {
-                    return self.bootrom[address as usize];
-                } else {
-                    return self.interrupt_table[address as usize];
-                }
-            }
-            0x100..0x8000 => {
+            0x0..0x8000 => {
                 // rom access
                 // todo - switchable rom banks
                 if self.bootrom_enabled && (address as usize) < self.bootrom.len() {
@@ -154,13 +145,7 @@ impl Memory {
         // verbose_println!("write addr: {:#X}, data: {:#X}", address, data);
 
         match address {
-            0x0..0x100 => {
-                if !self.bootrom_enabled {
-                    self.interrupt_table[address as usize] = data;
-                    // panic!("setting {:#X} to {:#X}", address, data)
-                }
-            }
-            0x100..0x8000 => {
+            0x0..0x8000 => {
                 // change this with MBC code...
                 // println!("tried to write {:#5X} at {:#X}", data, address);
             }
@@ -274,20 +259,11 @@ fn main() {
 
     let rom: ROM = fs::read(args.rom).expect("Could not load ROM");
     let bootrom: ROM = fs::read(args.bootrom).expect("Could not load BootROM");
-    let reg = Registers::default();
 
-    let mut cpu = CPU {
-        memory: Memory::init(bootrom, args.run_bootrom, rom),
-        reg,
-        last_instruction: 0x0,
-        last_instruction_addr: 0x0,
-        window,
-        gpu: GPU::default(),
-    };
+    let mut cpu = CPU::new(Memory::init(bootrom, args.run_bootrom, rom), window);
 
-    if args.run_bootrom {
-        cpu.reg.pc = 0x0;
-    } else {
+    if !args.run_bootrom {
+        cpu.reg.pc = 0x0100;
         cpu_ram_init(&mut cpu);
     }
 
diff --git a/src/processor/mod.rs b/src/processor/mod.rs
index 2e14452..6bff17f 100644
--- a/src/processor/mod.rs
+++ b/src/processor/mod.rs
@@ -38,6 +38,17 @@ const SPEEDUP: f64 = 1.;
 const FF04_SPEED: f64 = 16384.;
 
 impl CPU {
+    pub fn new(memory: Memory, window: Window) -> Self {
+        Self {
+            memory,
+            reg: Registers::default(),
+            last_instruction: 0x0,
+            last_instruction_addr: 0x0,
+            window,
+            gpu: GPU::default(),
+        }
+    }
+
     pub fn exec_next(&mut self) {
         self.last_instruction_addr = self.reg.pc;
         let opcode = self.next_opcode();
@@ -186,7 +197,7 @@ impl Default for Registers {
             de: 0x00D8,
             hl: 0x014D,
             sp: 0xFFFE,
-            pc: 0x0100,
+            pc: 0x0000,
         }
     }
 }