actually talk to mbcs

src/processor/memory.rs

@@ -169,18 +169,15 @@ impl Memory {
     }
 
     pub fn set(&mut self, address: Address, data: u8) {
-        // verbose_println!("write addr: {:#X}, data: {:#X}", address, data);
-
         match address {
             0x0..0x8000 => {
                 // change this with MBC code...
-                // println!("tried to write {:#5X} at {:#X}", data, address);
+                self.rom.set(address, data);
             }
             0x8000..0xA000 => {
                 self.vram[(address - 0x8000) as usize] = data;
             }
             0xA000..0xC000 => {
-                // panic!("switchable write");
                 // self.switchable_ram[(address - 0xA000) as usize] = data;
             }
             0xC000..0xE000 => {
@@ -197,15 +194,12 @@ impl Memory {
             }
             0xFF00..0xFF4C => {
                 self.set_io(address, data);
-                // verbose_print!("writing to addr {:#X}\r", address);
                 stdout().flush().unwrap();
             }
             0xFF50 => {
                 self.bootrom_enabled = false;
             }
-            0xFF4C..0xFF50 | 0xFF51..0xFF80 => {
+            0xFF4C..0xFF50 | 0xFF51..0xFF80 => {}
-                // println!("empty space 2 write: {:#X} to addr {:#X}", data, address);
-            }
             0xFF80..0xFFFF => {
                 self.cpu_ram[(address - 0xFF80) as usize] = data;
             }
@@ -275,7 +269,6 @@ impl Memory {
                 }
                 _ => {
                     self.io[addr_l] = data;
-                    // panic!("passed non-io address to io handler!");
                 }
             }
         }

src/processor/memory/rom.rs

@@ -39,4 +39,8 @@ impl ROM {
     pub(super) fn get(&self, address: Address) -> u8 {
         self.mbc.get(address)
     }
+
+    pub(super) fn set(&mut self, address: Address, data: u8) {
+        self.mbc.set(address, data);
+    }
 }