init cpu ram properly + other minor changes

src/main.rs

@@ -83,9 +83,10 @@ impl Memory {
                 // todo - switchable rom banks
                 if self.bootrom_enabled && (address as usize) < self.bootrom.len() {
                     return self.bootrom[address as usize];
-                }
+                } else {
                 return self.rom[address as usize];
             }
+            }
             0x8000..0xA000 => {
                 return self.vram[(address - 0x8000) as usize];
             }
@@ -169,6 +170,7 @@ impl Memory {
     }
 }
 
+#[derive(Clone, Copy)]
 pub struct State {
     af: Register,
     bc: Register,
@@ -208,6 +210,7 @@ fn main() {
         last_instruction: 0x0,
         last_instruction_addr: 0x0,
     };
+    cpu_ram_init(&mut cpu);
     #[allow(unused_variables)]
     let mut cycle_num = 0;
     match args.step_by {
@@ -253,3 +256,25 @@ fn print_cycles(cycles: &i32) {
     );
     stdout().flush().unwrap();
 }
+
+fn cpu_ram_init(cpu: &mut CPU) {
+    cpu.memory.set(0xFF10, 0x80);
+    cpu.memory.set(0xFF11, 0xBF);
+    cpu.memory.set(0xFF12, 0xF3);
+    cpu.memory.set(0xFF14, 0xBF);
+    cpu.memory.set(0xFF16, 0x3F);
+    cpu.memory.set(0xFF19, 0xBF);
+    cpu.memory.set(0xFF1A, 0x7F);
+    cpu.memory.set(0xFF1B, 0xFF);
+    cpu.memory.set(0xFF1C, 0x9F);
+    cpu.memory.set(0xFF1E, 0xBF);
+    cpu.memory.set(0xFF20, 0xFF);
+    cpu.memory.set(0xFF23, 0xBF);
+    cpu.memory.set(0xFF24, 0x77);
+    cpu.memory.set(0xFF25, 0xF3);
+    cpu.memory.set(0xFF26, 0xF1);
+    cpu.memory.set(0xFF40, 0x91);
+    cpu.memory.set(0xFF47, 0xFC);
+    cpu.memory.set(0xFF48, 0xFF);
+    cpu.memory.set(0xFF49, 0xFF);
+}