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work better when lcd is disabled + turn off bits in stat

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This commit is contained in:
Alex Janka 2023-02-09 11:10:33 +11:00
parent d5efdd6084
commit d6b95e6c6c
2 changed files with 11 additions and 12 deletions
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21
src/processor/gpu.rs
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@ -165,11 +165,10 @@ impl GPU {
impl CPU { impl CPU {
pub fn advance_gpu_clock(&mut self, steps: u8) { pub fn advance_gpu_clock(&mut self, steps: u8) {
let lcdc = self.get_lcdc();
if lcdc.enable {
let real_steps = (steps as usize) * 4; let real_steps = (steps as usize) * 4;
self.gpu.mode_clock += real_steps; self.gpu.mode_clock += real_steps;
let lcdc = self.get_lcdc();
match self.gpu.mode { match self.gpu.mode {
DrawMode::HBlank => { DrawMode::HBlank => {
// mode 0: hblank // mode 0: hblank
@ -177,7 +176,7 @@ impl CPU {
self.gpu.mode_clock = 0; self.gpu.mode_clock = 0;
self.gpu.scanline += 1; self.gpu.scanline += 1;
if self.gpu.scanline == 143 { if self.gpu.scanline == 143 {
self.enter_vblank(&lcdc); self.enter_vblank();
} else { } else {
self.gpu.mode = DrawMode::Mode2; self.gpu.mode = DrawMode::Mode2;
} }
@ -209,6 +208,11 @@ impl CPU {
} }
} }
} }
} else {
self.gpu.mode_clock = 0;
self.gpu.mode = DrawMode::VBlank;
self.gpu.scanline = 0;
}
self.set_lcd_status(); self.set_lcd_status();
} }
@ -247,14 +251,12 @@ impl CPU {
self.render_scanline(self.gpu.scanline, lcdc); self.render_scanline(self.gpu.scanline, lcdc);
} }
fn enter_vblank(&mut self, lcdc: &LCDC) { fn enter_vblank(&mut self) {
self.memory.update_pressed_keys(self.window.get_keys()); self.memory.update_pressed_keys(self.window.get_keys());
self.gpu.mode = DrawMode::VBlank; self.gpu.mode = DrawMode::VBlank;
if lcdc.enable {
self.render_window(); self.render_window();
self.memory.set(0xFF0F, set_bit(self.memory.get(0xFF0F), 0)); self.memory.set(0xFF0F, set_bit(self.memory.get(0xFF0F), 0));
} }
}
fn exit_vblank(&mut self) { fn exit_vblank(&mut self) {
self.gpu.mode = DrawMode::Mode2; self.gpu.mode = DrawMode::Mode2;
@ -277,15 +279,12 @@ impl CPU {
let mode_1_vblank = self.gpu.mode == DrawMode::VBlank; let mode_1_vblank = self.gpu.mode == DrawMode::VBlank;
let mode_0_hblank = self.gpu.mode == DrawMode::HBlank; let mode_0_hblank = self.gpu.mode == DrawMode::HBlank;
let mut irq = self.memory.get(0xFF0F);
if (lyc_eq_ly_enabled && lyc_eq_ly) if (lyc_eq_ly_enabled && lyc_eq_ly)
|| (mode_2_enabled && mode_2) || (mode_2_enabled && mode_2)
|| (mode_1_vblank_enabled && mode_1_vblank) || (mode_1_vblank_enabled && mode_1_vblank)
|| (mode_0_hblank_enabled && mode_0_hblank) || (mode_0_hblank_enabled && mode_0_hblank)
{ {
irq = set_bit(irq, 1); self.memory.set(0xFF0F, set_bit(self.memory.get(0xFF0F), 1));
self.memory.set(0xFF0F, irq);
} }
stat = set_or_clear_bit(stat, 2, lyc_eq_ly); stat = set_or_clear_bit(stat, 2, lyc_eq_ly);

2
src/processor/memory.rs
View file

@ -250,7 +250,7 @@ impl Memory {
} }
0xFF41 => { 0xFF41 => {
// mixed read/write // mixed read/write
self.io[addr_l] = self.io[addr_l] | (data & 0b1111000) self.io[addr_l] = (self.io[addr_l] & 0b00000111) | (data & 0b11111000)
} }
0xFF4D | 0xFF56 => { 0xFF4D | 0xFF56 => {
// cgb only // cgb only