all opcodes implemented-ish
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parent
e40bf4f786
commit
e6cbedc59b
238
src/processor.rs
238
src/processor.rs
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@ -1,4 +1,7 @@
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use std::ops::{BitAnd, BitOr, BitXor};
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use std::{
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mem::transmute,
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ops::{BitAnd, BitOr, BitXor},
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};
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use crate::{Inner, Memory, Register, State};
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@ -16,9 +19,9 @@ pub struct CPU {
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}
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impl CPU {
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pub fn exec_next(&mut self) -> u8 {
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pub fn exec_next(&mut self) {
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let opcode = self.next_opcode();
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unsafe { println!("exec {:#4X} from {:#4X}", opcode, self.state.pc.as_u16 - 1) };
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// unsafe { println!("exec {:#4X} from {:#4X}", opcode, self.state.pc.as_u16 - 1) };
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match opcode {
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0x0 => {
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// noop
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@ -76,7 +79,7 @@ impl CPU {
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.state
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.pc
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.as_u16
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.wrapping_add(self.ld_immediate_byte() as u16)
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.wrapping_add((as_signed(self.ld_immediate_byte()) as i16) as u16)
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},
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0x19 => unsafe {
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self.state.hl.as_u16 = self.state.hl.as_u16.wrapping_add(self.state.de.as_u16)
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@ -95,7 +98,11 @@ impl CPU {
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let jump_size = self.ld_immediate_byte();
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if self.get_flag(FLAGS::Z) == 0 {
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unsafe {
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self.state.pc.as_u16 = self.state.pc.as_u16.wrapping_add(jump_size as u16)
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self.state.pc.as_u16 = self
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.state
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.pc
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.as_u16
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.wrapping_add((as_signed(jump_size) as i16) as u16)
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}
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}
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}
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@ -118,7 +125,11 @@ impl CPU {
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let jump_size = self.ld_immediate_byte();
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if self.get_flag(FLAGS::Z) == 1 {
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unsafe {
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self.state.pc.as_u16 = self.state.pc.as_u16.wrapping_add(jump_size as u16)
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self.state.pc.as_u16 = self
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.state
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.pc
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.as_u16
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.wrapping_add((as_signed(jump_size) as i16) as u16)
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}
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}
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}
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@ -140,7 +151,11 @@ impl CPU {
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let jump_size = self.ld_immediate_byte();
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if self.get_flag(FLAGS::C) == 0 {
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unsafe {
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self.state.pc.as_u16 = self.state.pc.as_u16.wrapping_add(jump_size as u16)
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self.state.pc.as_u16 = self
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.state
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.pc
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.as_u16
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.wrapping_add((as_signed(jump_size) as i16) as u16)
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}
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}
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}
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@ -170,7 +185,11 @@ impl CPU {
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let jump_size = self.ld_immediate_byte();
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if self.get_flag(FLAGS::C) == 1 {
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unsafe {
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self.state.pc.as_u16 = self.state.pc.as_u16.wrapping_add(jump_size as u16)
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self.state.pc.as_u16 = self
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.state
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.pc
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.as_u16
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.wrapping_add((as_signed(jump_size) as i16) as u16)
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}
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}
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}
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@ -723,7 +742,10 @@ impl CPU {
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self.state.pc = maybe_next;
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}
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}
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0xCB => println!("Undefined behaviour: opcode CB"),
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0xCB => {
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let subop = self.ld_immediate_byte();
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self.cb_subop(subop);
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}
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0xCC => {
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let maybe_next = self.ld_immediate_word();
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if self.get_flag(FLAGS::Z) == 1 {
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@ -744,18 +766,192 @@ impl CPU {
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.wrapping_add(self.ld_immediate_byte() + self.get_flag(FLAGS::C))
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},
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0xCF => self.rst(0x08),
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0xEA => {
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0xD0 => unsafe {
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if self.get_flag(FLAGS::C) == 0 {
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let address = self.state.sp.as_u16;
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self.state.pc.as_u8s.left = self.memory.get(address);
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self.state.pc.as_u8s.right = self.memory.get(address + 1);
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self.state.sp.as_u16 = self.state.sp.as_u16.wrapping_add(2);
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}
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},
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0xD1 => unsafe {
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let address = self.state.sp.as_u16;
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self.state.de.as_u8s.left = self.memory.get(address);
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self.state.de.as_u8s.right = self.memory.get(address + 1);
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self.state.sp.as_u16 = self.state.sp.as_u16.wrapping_add(2);
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},
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0xD2 => {
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let word = self.ld_immediate_word();
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if self.get_flag(FLAGS::C) == 0 {
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self.state.pc = word;
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}
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}
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0xD3 => undefined(0xD3),
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0xD4 => {
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let maybe_next = self.ld_immediate_word();
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if self.get_flag(FLAGS::C) == 0 {
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self.push(self.state.pc);
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self.state.pc = maybe_next;
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}
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}
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0xD5 => self.push(self.state.de),
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0xD6 => unsafe {
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self.state.af.as_u8s.left = self
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.state
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.af
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.as_u8s
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.left
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.wrapping_sub(self.ld_immediate_byte())
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},
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0xD7 => self.rst(0x10),
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0xD8 => {
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if self.get_flag(FLAGS::C) == 1 {
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self.state.pc = self.pop_word()
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}
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}
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0xD9 => panic!("RETI: 0xD9"),
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0xDA => {
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let maybe_next = self.ld_immediate_word();
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if self.get_flag(FLAGS::C) == 1 {
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self.state.pc = maybe_next;
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}
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}
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0xDB => undefined(0xDB),
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0xDC => {
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let maybe_next = self.ld_immediate_word();
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if self.get_flag(FLAGS::C) == 1 {
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self.push(self.state.pc);
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self.state.pc = maybe_next;
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}
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}
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0xDD => undefined(0xDE),
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0xDE => unsafe {
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self.state.af.as_u8s.left = self
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.state
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.af
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.as_u8s
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.left
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.wrapping_sub(self.ld_immediate_byte() + self.get_flag(FLAGS::C))
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},
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0xDF => self.rst(0x18),
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0xE0 => {
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unsafe {
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let address = self.ld_immediate_word().as_u16;
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self.memory.set(address, self.state.af.as_u8s.left);
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let address = Register {
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as_u8s: Inner {
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left: self.ld_immediate_byte(),
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right: 0xFF,
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},
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};
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self.memory.set(address.as_u16, self.state.af.as_u8s.left);
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};
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}
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_ => {
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panic!("unimplemented opcode: {:#X}", opcode);
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0xE1 => unsafe {
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let address = self.state.sp.as_u16;
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self.state.hl.as_u8s.left = self.memory.get(address);
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self.state.hl.as_u8s.right = self.memory.get(address + 1);
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self.state.sp.as_u16 = self.state.sp.as_u16.wrapping_add(2);
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},
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0xE2 => {
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unsafe {
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let address = Register {
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as_u8s: Inner {
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left: self.state.bc.as_u8s.right,
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right: 0xFF,
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},
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};
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self.memory.set(address.as_u16, self.state.af.as_u8s.left);
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};
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}
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0xE3 => undefined(0xE3),
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0xE4 => undefined(0xE4),
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0xE5 => self.push(self.state.hl),
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0xE6 => unsafe {
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self.state.af.as_u8s.left =
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self.state.af.as_u8s.left.bitand(self.ld_immediate_byte())
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},
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0xE7 => self.rst(0x20),
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0xE8 => unsafe {
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self.state.sp.as_u16 = self
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.state
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.sp
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.as_u16
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.wrapping_add((as_signed(self.ld_immediate_byte()) as i16) as u16);
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},
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0xE9 => self.state.pc = self.state.hl,
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0xEA => unsafe {
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let address = self.ld_immediate_word().as_u16;
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self.memory.set(address, self.state.af.as_u8s.left);
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},
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0xEB => undefined(0xEB),
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0xEC => undefined(0xEC),
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0xED => undefined(0xED),
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0xEE => unsafe {
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self.state.af.as_u8s.left =
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self.state.af.as_u8s.left.bitxor(self.ld_immediate_byte())
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},
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0xEF => self.rst(0x28),
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0xF0 => {
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unsafe {
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let address = Register {
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as_u8s: Inner {
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left: self.ld_immediate_byte(),
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right: 0xFF,
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},
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};
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self.state.af.as_u8s.left = self.memory.get(address.as_u16);
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};
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}
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0xF1 => unsafe {
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let address = self.state.sp.as_u16;
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self.state.af.as_u8s.left = self.memory.get(address);
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self.state.af.as_u8s.right = self.memory.get(address + 1);
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self.state.sp.as_u16 = self.state.sp.as_u16.wrapping_add(2);
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},
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0xF2 => {
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unsafe {
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let address = Register {
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as_u8s: Inner {
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left: self.state.bc.as_u8s.right,
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right: 0xFF,
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},
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};
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self.state.af.as_u8s.left = self.memory.get(address.as_u16);
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};
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}
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0xF3 => panic!("DI IME instruction: 0xF3"),
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0xF4 => undefined(0xF4),
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0xF5 => self.push(self.state.af),
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0xF6 => unsafe {
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self.state.af.as_u8s.left =
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self.state.af.as_u8s.left.bitor(self.ld_immediate_byte())
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},
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0xF7 => self.rst(0x30),
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0xF8 => unsafe {
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self.state.hl.as_u16 = self
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.state
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.sp
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.as_u16
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.wrapping_add((as_signed(self.ld_immediate_byte()) as i16) as u16)
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},
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0xF9 => self.state.sp = self.state.hl,
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0xFA => unsafe {
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let address = self.ld_immediate_word().as_u16;
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self.state.af.as_u8s.left = self.memory.get(address);
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},
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0xFB => panic!("EI IME instruction: 0xFB"),
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0xFC => undefined(0xFC),
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0xFD => undefined(0xFD),
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0xFE => unsafe {
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if self.ld_immediate_byte() == self.state.af.as_u8s.left {
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self.set_flag(FLAGS::Z)
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}
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},
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0xFF => self.rst(0x38),
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};
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return opcode;
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}
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fn cb_subop(&mut self, subop: u8) {
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panic!("Unimplemented sub-opcode: {:#X}", subop);
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}
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fn next_opcode(&mut self) -> u8 {
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@ -839,3 +1035,13 @@ impl CPU {
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};
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}
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}
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fn undefined(opcode: u8) {
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println!("Undefined behaviour: opcode {:#X}", opcode);
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}
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fn as_signed(unsigned: u8) -> i8 {
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unsafe {
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return transmute(unsigned);
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}
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}
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