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fixes etc

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Alex Janka 2023-01-16 19:28:11 +11:00
parent 866d4ded80
commit edb348ec60
1 changed files with 14 additions and 7 deletions
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19
src/main.rs
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@ -28,8 +28,8 @@ type ROM = Vec<u8>;
#[derive(Clone, Copy)] #[derive(Clone, Copy)]
struct Inner { struct Inner {
right: u8,
left: u8, left: u8,
right: u8,
} }
#[derive(Clone, Copy)] #[derive(Clone, Copy)]
@ -42,6 +42,8 @@ pub struct Memory {
rom: ROM, rom: ROM,
vram: [u8; 8192], vram: [u8; 8192],
ram: [u8; 8192], ram: [u8; 8192],
switchable_ram: [u8; 8192],
cpu_ram: [u8; 128],
} }
impl Memory { impl Memory {
@ -50,6 +52,8 @@ impl Memory {
rom, rom,
vram: [0x0; 8192], vram: [0x0; 8192],
ram: [0x0; 8192], ram: [0x0; 8192],
switchable_ram: [0x0; 8192],
cpu_ram: [0x0; 128],
} }
} }
@ -64,7 +68,7 @@ impl Memory {
return self.vram[(address - 0x8000) as usize]; return self.vram[(address - 0x8000) as usize];
} }
0xA000..0xC000 => { 0xA000..0xC000 => {
panic!("switchable ram bank"); return self.switchable_ram[(address - 0xA000) as usize];
} }
0xC000..0xE000 => { 0xC000..0xE000 => {
return self.ram[(address - 0xC000) as usize]; return self.ram[(address - 0xC000) as usize];
@ -85,7 +89,7 @@ impl Memory {
panic!("empty"); panic!("empty");
} }
0xFF80..0xFFFF => { 0xFF80..0xFFFF => {
panic!("internal ram"); return self.cpu_ram[(address - 0xFF80) as usize];
} }
0xFFFF => { 0xFFFF => {
panic!("interrupt enable register"); panic!("interrupt enable register");
@ -97,13 +101,13 @@ impl Memory {
match address { match address {
0x0..0x8000 => { 0x0..0x8000 => {
// change this with MBC code... // change this with MBC code...
println!("tried to write to rom?"); println!("tried to write {:#5X} at {:#X}", data, address);
} }
0x8000..0xA000 => { 0x8000..0xA000 => {
self.vram[(address - 0x8000) as usize] = data; self.vram[(address - 0x8000) as usize] = data;
} }
0xA000..0xC000 => { 0xA000..0xC000 => {
panic!("switchable ram bank"); self.switchable_ram[(address - 0xA000) as usize] = data;
} }
0xC000..0xE000 => { 0xC000..0xE000 => {
self.ram[(address - 0xC000) as usize] = data; self.ram[(address - 0xC000) as usize] = data;
@ -124,7 +128,7 @@ impl Memory {
panic!("empty"); panic!("empty");
} }
0xFF80..0xFFFF => { 0xFF80..0xFFFF => {
panic!("internal ram"); self.cpu_ram[(address - 0xFF80) as usize] = data;
} }
0xFFFF => { 0xFFFF => {
panic!("interrupt enable register"); panic!("interrupt enable register");
@ -174,8 +178,11 @@ fn main() {
state, state,
}; };
loop { loop {
for _ in 0..10 {
cpu.exec_next(); cpu.exec_next();
} }
pause();
}
} }
#[allow(dead_code)] #[allow(dead_code)]