diff --git a/src/processor/mod.rs b/src/processor/mod.rs
index d3adc3c..81b1c13 100644
--- a/src/processor/mod.rs
+++ b/src/processor/mod.rs
@@ -114,7 +114,7 @@ impl CPU {
     }
 
     fn handle_interrupts(&mut self) -> u8 {
-        if self.memory.ime {
+        if self.memory.ime || self.halted {
             let req_and_enabled = self.memory.get(0xFF0F) & self.memory.get(0xFFFF);
             // all interrupts should last 5 cycles?
             if get_bit(req_and_enabled, 0) {