346 lines
9.4 KiB
Rust
346 lines
9.4 KiB
Rust
#![feature(exclusive_range_pattern)]
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mod processor;
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use clap::Parser;
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use processor::CPU;
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use std::{
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fs,
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io::{self, stdout, Write},
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};
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/// Simple program to greet a person
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#[derive(Parser, Debug)]
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#[command(author, version, about, long_about = None)]
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struct Args {
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/// ROM path
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#[arg(short, long)]
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rom: String,
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/// BootROM path
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#[arg(short, long)]
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bootrom: String,
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/// Just run BootROM
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#[arg(long)]
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run_bootrom: bool,
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/// Step emulation by...
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#[arg(long)]
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step_by: Option<usize>,
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}
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type Address = u16;
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type ROM = Vec<u8>;
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#[derive(Clone, Copy)]
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struct Inner {
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left: u8,
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right: u8,
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}
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#[derive(Clone, Copy)]
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union Register {
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as_u8s: Inner,
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as_u16: u16,
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}
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#[allow(dead_code)]
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pub struct Memory {
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bootrom: ROM,
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bootrom_enabled: bool,
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interrupt_table: [u8; 256],
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rom: ROM,
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vram: [u8; 8192],
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ram: [u8; 8192],
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switchable_ram: [u8; 8192],
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cpu_ram: [u8; 128],
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oam: [u8; 160],
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interrupts: u8,
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ime: bool,
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io: [u8; 76],
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}
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impl Memory {
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fn init(bootrom: ROM, bootrom_enabled: bool, rom: ROM) -> Self {
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Self {
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bootrom,
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bootrom_enabled,
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interrupt_table: [0xFF; 256],
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rom,
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vram: [0x0; 8192],
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ram: [0x0; 8192],
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switchable_ram: [0x0; 8192],
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cpu_ram: [0x0; 128],
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oam: [0x0; 160],
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interrupts: 0x0,
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ime: false,
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io: [0xFF; 76],
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}
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}
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fn get(&self, address: Address) -> u8 {
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match address {
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0x0..0x100 => {
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if self.bootrom_enabled {
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return self.bootrom[address as usize];
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} else {
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return self.interrupt_table[address as usize];
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}
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}
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0x100..0x8000 => {
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// rom access
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// todo - switchable rom banks
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if self.bootrom_enabled && (address as usize) < self.bootrom.len() {
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return self.bootrom[address as usize];
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} else {
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return self.rom[address as usize];
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}
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}
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0x8000..0xA000 => {
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return self.vram[(address - 0x8000) as usize];
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}
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0xA000..0xC000 => {
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0xFF
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}
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0xC000..0xE000 => {
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return self.ram[(address - 0xC000) as usize];
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}
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0xE000..0xFE00 => {
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return self.ram[(address - 0xE000) as usize];
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}
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0xFE00..0xFEA0 => {
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return self.oam[(address - 0xFE00) as usize];
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}
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0xFEA0..0xFF00 => {
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return 0x0;
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}
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0xFF00..0xFF4C => {
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return self.io[(address - 0xFF00) as usize];
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}
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0xFF4C..0xFF80 => {
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// println!("empty space 2 read");
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return 0xFF;
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}
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0xFF80..0xFFFF => {
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return self.cpu_ram[(address - 0xFF80) as usize];
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}
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0xFFFF => {
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return self.interrupts;
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}
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}
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}
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fn set(&mut self, address: Address, data: u8) {
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match address {
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0x0..0x100 => {
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if !self.bootrom_enabled {
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self.interrupt_table[address as usize] = data;
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// panic!("setting {:#X} to {:#X}", address, data)
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}
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}
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0x100..0x8000 => {
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// change this with MBC code...
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// println!("tried to write {:#5X} at {:#X}", data, address);
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}
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0x8000..0xA000 => {
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self.vram[(address - 0x8000) as usize] = data;
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}
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0xA000..0xC000 => {
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// panic!("switchable write");
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// self.switchable_ram[(address - 0xA000) as usize] = data;
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}
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0xC000..0xE000 => {
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self.ram[(address - 0xC000) as usize] = data;
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}
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0xE000..0xFE00 => {
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self.ram[(address - 0xE000) as usize] = data;
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}
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0xFE00..0xFEA0 => {
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self.oam[(address - 0xFE00) as usize] = data;
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}
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0xFEA0..0xFF00 => {
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// println!("empty space write: {:#X} to addr {:#X}", data, address);
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}
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0xFF00..0xFF4C => {
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print!("writing to addr {:#X}\r", address);
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stdout().flush().unwrap();
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if address == 0xFF02 && data == 0x81 {
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print!("{}", self.get(0xFF01) as char);
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stdout().flush().unwrap();
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}
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self.io[(address - 0xFF00) as usize] = data;
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}
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0xFF4C..0xFF80 => {
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// println!("empty space 2 write: {:#X} to addr {:#X}", data, address);
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}
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0xFF80..0xFFFF => {
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self.cpu_ram[(address - 0xFF80) as usize] = data;
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}
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0xFFFF => {
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println!("interrupts set to {:#b}", data);
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println!(" / {:#X}", data);
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self.interrupts = data;
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}
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}
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}
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}
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#[derive(Clone, Copy)]
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pub struct State {
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af: Register,
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bc: Register,
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de: Register,
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hl: Register,
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sp: Register,
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pc: Register,
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}
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impl Default for State {
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fn default() -> Self {
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// default post-bootrom values
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Self {
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af: Register { as_u16: 0x00B0 },
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// af: Register { as_u16: 0x01B0 },
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bc: Register { as_u16: 0x0013 },
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de: Register { as_u16: 0x00D8 },
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hl: Register { as_u16: 0x014D },
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sp: Register { as_u16: 0xFFFE },
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pc: Register { as_u16: 0x0100 },
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}
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}
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}
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static mut PAUSE_ENABLED: bool = false;
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static mut PAUSE_QUEUED: bool = false;
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fn main() {
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let args = Args::parse();
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let rom: ROM = fs::read(args.rom).expect("Could not load ROM");
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let bootrom: ROM = fs::read(args.bootrom).expect("Could not load BootROM");
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let mut state = State::default();
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if args.run_bootrom {
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state.pc = Register { as_u16: 0x0 };
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}
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let mut cpu = CPU {
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memory: Memory::init(bootrom, args.run_bootrom, rom),
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state,
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last_instruction: 0x0,
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last_instruction_addr: 0x0,
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};
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cpu_ram_init(&mut cpu);
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#[allow(unused_variables)]
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let mut cycle_num = 0;
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let mut instructions_seen = vec![];
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let mut last_state = cpu.state.clone();
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let mut next_state: State;
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match args.step_by {
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Some(step_size) => loop {
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for _ in 0..step_size {
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cycle_num += 1;
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cpu.exec_next();
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println!(
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"exec {:#4X} from {:#4X}",
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cpu.last_instruction, cpu.last_instruction_addr
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);
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}
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print!(
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" ...{} cycles - press enter to continue\r",
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cycle_num
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);
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stdout().flush().unwrap();
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pause();
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},
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None => loop {
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let will_pause;
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unsafe {
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will_pause = PAUSE_QUEUED.clone();
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}
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cycle_num += 1;
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// print_cycles(&cycle_num);
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cpu.exec_next();
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unsafe {
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next_state = cpu.state;
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if !PAUSE_ENABLED {
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if next_state.pc.as_u16 >= 0x100 {
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PAUSE_ENABLED = true;
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}
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}
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last_state = next_state;
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if will_pause {
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pause();
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}
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}
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match instructions_seen.contains(&cpu.last_instruction) {
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true => {}
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false => {
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// println!("new instruction enountered: {:#X}", cpu.last_instruction);
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instructions_seen.push(cpu.last_instruction);
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}
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}
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},
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}
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}
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#[allow(dead_code)]
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fn pause() {
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unsafe {
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if PAUSE_ENABLED {
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let line = &mut String::new();
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io::stdin().read_line(line).unwrap();
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PAUSE_QUEUED = !line.contains("continue");
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}
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}
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}
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#[allow(dead_code)]
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fn print_cycles(cycles: &i32) {
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if *cycles % 456789 != 0 {
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return;
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}
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let instructions_per_second = 400000;
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print!(
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"cycle {} - approx {} seconds on real hardware\r",
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cycles,
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cycles / instructions_per_second
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);
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stdout().flush().unwrap();
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}
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fn cpu_ram_init(cpu: &mut CPU) {
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cpu.memory.set(0xFF10, 0x80);
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cpu.memory.set(0xFF11, 0xBF);
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cpu.memory.set(0xFF12, 0xF3);
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cpu.memory.set(0xFF14, 0xBF);
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cpu.memory.set(0xFF16, 0x3F);
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cpu.memory.set(0xFF19, 0xBF);
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cpu.memory.set(0xFF1A, 0x7F);
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cpu.memory.set(0xFF1B, 0xFF);
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cpu.memory.set(0xFF1C, 0x9F);
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cpu.memory.set(0xFF1E, 0xBF);
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cpu.memory.set(0xFF20, 0xFF);
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cpu.memory.set(0xFF23, 0xBF);
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cpu.memory.set(0xFF24, 0x77);
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cpu.memory.set(0xFF25, 0xF3);
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cpu.memory.set(0xFF26, 0xF1);
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cpu.memory.set(0xFF40, 0x91);
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cpu.memory.set(0xFF47, 0xFC);
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cpu.memory.set(0xFF48, 0xFF);
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cpu.memory.set(0xFF49, 0xFF);
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}
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#[allow(dead_code)]
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fn swap_rom_endian(rom: &ROM) -> ROM {
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rom.chunks(2)
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.map(|l| {
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let mut m = l.to_owned();
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m.reverse();
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m
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})
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.flatten()
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.collect()
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}
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