2019-02-14 09:42:24 +11:00
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#![no_std]
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2021-04-09 15:57:30 +10:00
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#![no_main]
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#![feature(isa_attribute)]
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2021-05-02 10:38:52 +10:00
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use gba::prelude::*;
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2019-02-14 09:42:24 +11:00
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const BLACK: Color = Color::from_rgb(0, 0, 0);
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const RED: Color = Color::from_rgb(31, 0, 0);
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const GREEN: Color = Color::from_rgb(0, 31, 0);
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const BLUE: Color = Color::from_rgb(0, 0, 31);
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const YELLOW: Color = Color::from_rgb(31, 31, 0);
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const PINK: Color = Color::from_rgb(31, 0, 31);
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#[panic_handler]
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fn panic(_info: &core::panic::PanicInfo) -> ! {
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loop {}
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}
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fn start_timers() {
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let init_val: u16 = u32::wrapping_sub(0x1_0000, 64) as u16;
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2021-04-09 15:57:30 +10:00
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const TIMER_SETTINGS: TimerControl =
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TimerControl::new().with_irq_on_overflow(true).with_enabled(true);
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2019-02-14 09:42:24 +11:00
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2021-04-09 15:57:30 +10:00
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TIMER0_RELOAD.write(init_val);
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TIMER0_CONTROL.write(TIMER_SETTINGS.with_prescaler_selection(3));
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TIMER1_RELOAD.write(init_val);
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TIMER1_CONTROL.write(TIMER_SETTINGS.with_prescaler_selection(1));
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2019-02-14 09:42:24 +11:00
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}
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2021-04-09 15:57:30 +10:00
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#[no_mangle]
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fn main() -> ! {
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DISPCNT.write(DisplayControl::new().with_display_mode(3).with_display_bg2(true));
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mode3::dma3_clear_to(BLACK);
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2019-02-14 09:42:24 +11:00
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// Set the IRQ handler to use.
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2021-04-09 15:57:30 +10:00
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unsafe { USER_IRQ_HANDLER.write(Some(irq_handler_a32)) };
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2019-02-14 09:42:24 +11:00
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// Enable all interrupts that are set in the IE register.
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2021-04-09 15:57:30 +10:00
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unsafe { IME.write(true) };
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2019-02-14 09:42:24 +11:00
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// Request that VBlank, HBlank and VCount will generate IRQs.
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2021-04-09 15:57:30 +10:00
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const DISPLAY_SETTINGS: DisplayStatus = DisplayStatus::new()
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.with_vblank_irq_enabled(true)
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.with_hblank_irq_enabled(true)
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.with_vcount_irq_enabled(true);
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2019-02-14 09:42:24 +11:00
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DISPSTAT.write(DISPLAY_SETTINGS);
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// Start two timers with overflow IRQ generation.
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start_timers();
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loop {
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2021-04-09 15:57:30 +10:00
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let this_frame_keys: Keys = KEYINPUT.read().into();
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2019-02-14 09:42:24 +11:00
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// The VBlank IRQ must be enabled at minimum, or else the CPU will halt
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// at the call to vblank_interrupt_wait() as the VBlank IRQ will never
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// be triggered.
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2021-04-09 15:57:30 +10:00
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let mut flags = InterruptFlags::new().with_vblank(true);
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2019-02-14 09:42:24 +11:00
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// Enable interrupts based on key input.
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if this_frame_keys.a() {
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flags = flags.with_hblank(true);
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}
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if this_frame_keys.b() {
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2021-04-09 15:57:30 +10:00
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flags = flags.with_vcount(true);
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2019-02-14 09:42:24 +11:00
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}
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if this_frame_keys.l() {
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flags = flags.with_timer0(true);
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}
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if this_frame_keys.r() {
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flags = flags.with_timer1(true);
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}
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2021-04-01 13:22:42 +11:00
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unsafe { IE.write(flags) };
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2019-02-14 09:42:24 +11:00
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// Puts the CPU into low power mode until a VBlank IRQ is received. This
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// will yield considerably better power efficiency as opposed to spin
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// waiting.
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2021-04-09 15:57:30 +10:00
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unsafe { VBlankIntrWait() };
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2019-02-14 09:42:24 +11:00
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}
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}
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static mut PIXEL: usize = 0;
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fn write_pixel(color: Color) {
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unsafe {
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2021-04-09 15:57:30 +10:00
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(0x0600_0000 as *mut Color).wrapping_offset(PIXEL as isize).write_volatile(color);
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PIXEL += 1;
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if PIXEL == (mode3::WIDTH * mode3::HEIGHT) {
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PIXEL = 0;
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}
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2019-02-14 09:42:24 +11:00
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}
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}
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2021-04-09 15:57:30 +10:00
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#[instruction_set(arm::a32)]
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extern "C" fn irq_handler_a32() {
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// we just use this a32 function to jump over back to t32 code.
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irq_handler_t32()
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}
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fn irq_handler_t32() {
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2021-04-12 09:41:08 +10:00
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// disable Interrupt Master Enable to prevent an interrupt during the handler
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unsafe { IME.write(false) };
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2021-04-09 15:57:30 +10:00
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2021-04-12 09:41:08 +10:00
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// read which interrupts are pending, and "filter" the selection by which are
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// supposed to be enabled.
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let which_interrupts_to_handle = IRQ_PENDING.read() & IE.read();
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// read the current IntrWait value. It sorta works like a running total, so
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// any interrupts we process we'll enable in this value, which we write back
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// at the end.
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let mut intr_wait_flags = INTR_WAIT_ACKNOWLEDGE.read();
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if which_interrupts_to_handle.vblank() {
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2019-02-14 09:42:24 +11:00
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vblank_handler();
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2021-04-12 09:41:08 +10:00
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intr_wait_flags.set_vblank(true);
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2019-02-14 09:42:24 +11:00
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}
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2021-04-12 09:41:08 +10:00
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if which_interrupts_to_handle.hblank() {
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2019-02-14 09:42:24 +11:00
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hblank_handler();
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2021-04-12 09:41:08 +10:00
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intr_wait_flags.set_hblank(true);
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2019-02-14 09:42:24 +11:00
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}
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2021-04-12 09:41:08 +10:00
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if which_interrupts_to_handle.vcount() {
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2021-04-09 15:57:30 +10:00
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vcount_handler();
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2021-04-12 09:41:08 +10:00
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intr_wait_flags.set_vcount(true);
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2019-02-14 09:42:24 +11:00
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}
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2021-04-12 09:41:08 +10:00
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if which_interrupts_to_handle.timer0() {
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2019-02-14 09:42:24 +11:00
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timer0_handler();
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2021-04-12 09:41:08 +10:00
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intr_wait_flags.set_timer0(true);
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2019-02-14 09:42:24 +11:00
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}
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2021-04-12 09:41:08 +10:00
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if which_interrupts_to_handle.timer1() {
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2019-02-14 09:42:24 +11:00
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timer1_handler();
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2021-04-12 09:41:08 +10:00
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intr_wait_flags.set_timer1(true);
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2019-02-14 09:42:24 +11:00
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}
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2021-04-12 09:41:08 +10:00
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// acknowledge that we did stuff.
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IRQ_ACKNOWLEDGE.write(which_interrupts_to_handle);
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// write out any IntrWait changes.
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unsafe { INTR_WAIT_ACKNOWLEDGE.write(intr_wait_flags) };
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// re-enable as we go out.
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unsafe { IME.write(true) };
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2019-02-14 09:42:24 +11:00
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}
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fn vblank_handler() {
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write_pixel(BLUE);
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}
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fn hblank_handler() {
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write_pixel(GREEN);
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}
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2021-04-09 15:57:30 +10:00
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fn vcount_handler() {
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2019-02-14 09:42:24 +11:00
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write_pixel(RED);
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}
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fn timer0_handler() {
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write_pixel(YELLOW);
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}
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fn timer1_handler() {
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write_pixel(PINK);
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}
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