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output registers for a GbaCell read are lateout.

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This commit is contained in:
Lokathor 2022-10-17 15:49:38 -06:00
parent 0fe5422674
commit c4daa3e937
1 changed files with 3 additions and 3 deletions
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6
src/gba_cell.rs
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@ -100,7 +100,7 @@ where
let val: u32;
core::arch::asm!(
"ldr {r}, [{addr}]",
r = out(reg) val,
r = lateout(reg) val,
addr = in(reg) self.get_ptr(),
options(readonly, preserves_flags, nostack)
);
@ -110,7 +110,7 @@ where
let val: u16;
core::arch::asm!(
"ldrh {r}, [{addr}]",
r = out(reg) val,
r = lateout(reg) val,
addr = in(reg) self.get_ptr(),
options(readonly, preserves_flags, nostack)
);
@ -120,7 +120,7 @@ where
let val: u8;
core::arch::asm!(
"ldrb {r}, [{addr}]",
r = out(reg) val,
r = lateout(reg) val,
addr = in(reg) self.get_ptr(),
options(readonly, preserves_flags, nostack)
);