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output registers for a GbaCell read are lateout.
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parent
0fe5422674
commit
c4daa3e937
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@ -100,7 +100,7 @@ where
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let val: u32;
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let val: u32;
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core::arch::asm!(
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core::arch::asm!(
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"ldr {r}, [{addr}]",
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"ldr {r}, [{addr}]",
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r = out(reg) val,
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r = lateout(reg) val,
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addr = in(reg) self.get_ptr(),
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addr = in(reg) self.get_ptr(),
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options(readonly, preserves_flags, nostack)
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options(readonly, preserves_flags, nostack)
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);
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);
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@ -110,7 +110,7 @@ where
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let val: u16;
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let val: u16;
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core::arch::asm!(
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core::arch::asm!(
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"ldrh {r}, [{addr}]",
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"ldrh {r}, [{addr}]",
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r = out(reg) val,
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r = lateout(reg) val,
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addr = in(reg) self.get_ptr(),
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addr = in(reg) self.get_ptr(),
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options(readonly, preserves_flags, nostack)
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options(readonly, preserves_flags, nostack)
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);
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);
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@ -120,7 +120,7 @@ where
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let val: u8;
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let val: u8;
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core::arch::asm!(
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core::arch::asm!(
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"ldrb {r}, [{addr}]",
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"ldrb {r}, [{addr}]",
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r = out(reg) val,
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r = lateout(reg) val,
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addr = in(reg) self.get_ptr(),
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addr = in(reg) self.get_ptr(),
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options(readonly, preserves_flags, nostack)
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options(readonly, preserves_flags, nostack)
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);
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);
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