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@ -48,14 +48,18 @@
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//! TIMER0_RELOAD.write(x.wrapping_neg());
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//! ```
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//!
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//! ## Timer Tips
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//! ## Using Cascade To Pause A Timer
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//!
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//! When a timer goes from disabled to enabled it will reset the counter value
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//! to the reload value. If you want to temporarily pause a timer *without*
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//! having the counter value get reset when you resume the timer you can instead
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//! set the `cascade` bit of the timer while the next lower timer is disabled.
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//! This keeps the timer active but prevents it from ticking. Note that this
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//! doesn't work for timer 0 because that timer ignores the cascade bit.
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//! set the `cascade` bit of the timer while the next lower timer is
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//! **disabled**. This keeps the timer "active" but prevents it from ticking.
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//! When you turn off cascade mode the timer will resume ticking from the
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//! current counter value.
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//!
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//! Note that this doesn't work for timer 0, because that timer ignores the
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//! cascade bit.
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use crate::macros::{pub_const_fn_new_zeroed, u16_bool_field, u16_enum_field};
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@ -74,14 +78,20 @@ pub enum TimerScale {
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/// Approximately 3.815 microseconds
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_64 = 1,
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/// Approximately 15.26 microseconds
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///
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/// **Hint:** With a reload value of 0, this timer scale will overflow
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/// exactly once per second.
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_256 = 2,
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/// Approximately 61.04 microseconds
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///
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/// **Hint:** With a reload value of `0x4000_u16.wrapping_neg()`,
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/// this timer scale will overflow exactly once per second.
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_1024 = 3,
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}
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/// Timer configuration bits.
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///
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/// * `prescale` is how many CPU cycles per tick
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/// * `scale` is how many CPU cycles per tick
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/// * `cascade` will override the prescale value and instead tick the timer once
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/// per overflow of the next lower timer. Timer 0 ignores the cascade bit.
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/// * `overflow_irq` will cause an IRQ to be sent each overflow.
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