Clean up ScopedFtz conditional compilation for MIRI
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4c87db906a
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@ -203,19 +203,20 @@ struct ScopedFtz {
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impl ScopedFtz {
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fn enable() -> Self {
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#[cfg(not(miri))]
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cfg_if::cfg_if! {
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if #[cfg(all(target_feature = "sse", not(miri)))] {
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if #[cfg(target_feature = "sse")] {
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let mode = unsafe { std::arch::x86_64::_MM_GET_FLUSH_ZERO_MODE() };
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let should_disable_again = mode != std::arch::x86_64::_MM_FLUSH_ZERO_ON;
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if should_disable_again {
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unsafe { std::arch::x86_64::_MM_SET_FLUSH_ZERO_MODE(std::arch::x86_64::_MM_FLUSH_ZERO_ON) };
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}
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Self {
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return Self {
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should_disable_again,
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_send_sync_marker: PhantomData,
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}
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} else if #[cfg(all(target_arch = "aarch64", not(miri)))] {
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} else if #[cfg(target_arch = "aarch64")] {
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// There are no convient intrinsics to change the FTZ settings on AArch64, so this
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// requires inline assembly:
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// https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/FPCR--Floating-point-Control-Register
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@ -227,17 +228,17 @@ impl ScopedFtz {
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unsafe { std::arch::asm!("msr fpcr, {}", in(reg) fpcr | AARCH64_FTZ_BIT) };
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}
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Self {
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return Self {
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should_disable_again,
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_send_sync_marker: PhantomData,
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}
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} else {
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Self {
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should_disable_again: false,
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_send_sync_marker: PhantomData,
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}
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}
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}
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Self {
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should_disable_again: false,
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_send_sync_marker: PhantomData,
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}
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}
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}
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