2021-04-25 18:51:46 +10:00
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//! Universal Asynchronous Receiver Transmitter (UART)
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2021-01-26 07:42:43 +11:00
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// See [Chapter 4 Section 2](https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf) for more details
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2021-04-25 18:51:46 +10:00
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use core::convert::Infallible;
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use core::ops::Deref;
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2021-05-02 16:42:51 +10:00
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use embedded_time::fixed_point::FixedPoint;
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2021-04-25 18:51:46 +10:00
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use embedded_time::rate::Baud;
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use embedded_time::rate::Hertz;
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2021-05-02 16:41:20 +10:00
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2021-05-02 16:42:51 +10:00
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use embedded_hal::serial::{Read, Write};
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2021-05-02 16:41:20 +10:00
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2021-05-02 16:42:51 +10:00
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use nb::Error::{Other, WouldBlock};
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2021-04-25 18:51:46 +10:00
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2021-04-26 04:24:56 +10:00
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use crate::pac::{
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2021-05-02 16:42:51 +10:00
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uart0::{uartlcr_h::W as UART_LCR_H_Writer, RegisterBlock},
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UART0, UART1,
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2021-04-26 04:24:56 +10:00
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};
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2021-04-25 18:51:46 +10:00
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2021-04-26 17:14:32 +10:00
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/// Error type for UART operations.
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2021-04-27 05:25:52 +10:00
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#[derive(Debug)]
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2021-04-26 17:14:32 +10:00
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pub enum Error {
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/// Bad argument : when things overflow, ...
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2021-05-02 16:42:51 +10:00
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BadArgument,
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2021-04-26 17:14:32 +10:00
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}
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2021-05-02 16:27:29 +10:00
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/// When there's a read error.
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pub struct ReadError<'err> {
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/// The type of error
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pub err_type: ReadErrorType,
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/// Reference to the data that was read but eventually discared because of the error.
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2021-05-02 16:42:51 +10:00
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pub discared: &'err [u8],
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2021-05-02 16:27:29 +10:00
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}
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/// Possible types of read errors. See Chapter 4, Section 2 §8 - Table 436: "UARTDR Register"
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pub enum ReadErrorType {
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/// Triggered when the FIFO (or shift-register) is overflowed.
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Overrun,
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/// Triggered when a break is received
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Break,
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/// Triggered when there is a parity mismatch between what's received and our settings.
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Parity,
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/// Triggered when the received character didn't have a valid stop bit.
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2021-05-02 16:42:51 +10:00
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Framing,
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2021-05-02 16:27:29 +10:00
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}
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2021-04-25 18:51:46 +10:00
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/// State of the UART Peripheral.
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pub trait State {}
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/// Trait to handle both underlying devices (UART0 & UART1)
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2021-05-09 17:53:22 +10:00
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pub trait UartDevice: Deref<Target = RegisterBlock> {}
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2021-04-25 18:51:46 +10:00
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2021-05-09 17:53:22 +10:00
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impl UartDevice for UART0 {}
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impl UartDevice for UART1 {}
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2021-04-25 18:51:46 +10:00
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/// UART is enabled.
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pub struct Enabled;
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/// UART is disabled.
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pub struct Disabled;
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impl State for Enabled {}
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impl State for Disabled {}
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/// Data bits
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pub enum DataBits {
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/// 5 bits
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Five,
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/// 6 bits
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Six,
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/// 7 bits
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Seven,
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/// 8 bits
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2021-05-02 16:42:51 +10:00
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Eight,
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}
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/// Stop bits
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pub enum StopBits {
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/// 1 bit
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One,
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/// 2 bits
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2021-05-02 16:42:51 +10:00
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Two,
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}
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/// Parity
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/// The "none" state of parity is represented with the Option type (None).
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pub enum Parity {
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/// Odd parity
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Odd,
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/// Even parity
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2021-05-02 16:42:51 +10:00
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Even,
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2021-04-25 18:51:46 +10:00
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}
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/// A struct holding the configuration for an UART device.
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2021-05-09 17:53:22 +10:00
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pub struct UartConfig {
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2021-04-25 18:51:46 +10:00
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baudrate: Baud,
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data_bits: DataBits,
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stop_bits: StopBits,
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2021-05-02 16:42:51 +10:00
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parity: Option<Parity>,
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2021-04-25 18:51:46 +10:00
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}
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/// Common configurations for UART.
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pub mod common_configs {
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2021-05-09 17:53:22 +10:00
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use super::{DataBits, StopBits, UartConfig};
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2021-04-25 18:51:46 +10:00
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use embedded_time::rate::Baud;
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/// 9600 baud, 8 data bits, no parity, 1 stop bit
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2021-05-09 17:53:22 +10:00
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pub const _9600_8_N_1: UartConfig = UartConfig {
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2021-04-25 18:51:46 +10:00
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baudrate: Baud(9600),
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data_bits: DataBits::Eight,
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stop_bits: StopBits::One,
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parity: None,
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2021-04-25 18:51:46 +10:00
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};
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/// 19200 baud, 8 data bits, no parity, 1 stop bit
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2021-05-09 17:53:22 +10:00
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pub const _19200_8_N_1: UartConfig = UartConfig {
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2021-04-25 18:51:46 +10:00
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baudrate: Baud(19200),
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data_bits: DataBits::Eight,
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stop_bits: StopBits::One,
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2021-05-02 16:42:51 +10:00
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parity: None,
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2021-04-25 18:51:46 +10:00
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};
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/// 38400 baud, 8 data bits, no parity, 1 stop bit
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2021-05-09 17:53:22 +10:00
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pub const _38400_8_N_1: UartConfig = UartConfig {
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2021-04-25 18:51:46 +10:00
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baudrate: Baud(38400),
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data_bits: DataBits::Eight,
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stop_bits: StopBits::One,
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2021-05-02 16:42:51 +10:00
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parity: None,
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2021-04-25 18:51:46 +10:00
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};
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/// 57600 baud, 8 data bits, no parity, 1 stop bit
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2021-05-09 17:53:22 +10:00
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pub const _57600_8_N_1: UartConfig = UartConfig {
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2021-04-25 18:51:46 +10:00
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baudrate: Baud(57600),
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data_bits: DataBits::Eight,
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stop_bits: StopBits::One,
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parity: None,
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2021-04-25 18:51:46 +10:00
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};
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/// 115200 baud, 8 data bits, no parity, 1 stop bit
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2021-05-09 17:53:22 +10:00
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pub const _115200_8_N_1: UartConfig = UartConfig {
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2021-04-25 18:51:46 +10:00
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baudrate: Baud(115200),
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data_bits: DataBits::Eight,
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stop_bits: StopBits::One,
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2021-05-02 16:42:51 +10:00
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parity: None,
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2021-04-25 18:51:46 +10:00
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};
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}
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/// An UART Peripheral based on an underlying UART device.
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2021-05-09 17:53:22 +10:00
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pub struct UartPeripheral<S: State, D: UartDevice> {
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2021-04-25 18:51:46 +10:00
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device: D,
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_state: S,
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config: UartConfig,
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2021-05-02 16:42:51 +10:00
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effective_baudrate: Baud,
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2021-04-25 18:51:46 +10:00
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}
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2021-05-09 17:53:22 +10:00
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impl<S: State, D: UartDevice> UartPeripheral<S, D> {
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fn transition<To: State>(self, state: To) -> UartPeripheral<To, D> {
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UartPeripheral {
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2021-04-25 18:51:46 +10:00
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device: self.device,
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config: self.config,
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effective_baudrate: self.effective_baudrate,
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2021-05-02 16:42:51 +10:00
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_state: state,
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2021-04-25 18:51:46 +10:00
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}
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}
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/// Releases the underlying device.
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2021-05-02 16:42:51 +10:00
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pub fn free(self) -> D {
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2021-04-25 18:51:46 +10:00
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self.device
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}
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}
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2021-05-09 17:53:22 +10:00
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impl<D: UartDevice> UartPeripheral<Disabled, D> {
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2021-04-25 18:51:46 +10:00
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/// Enables the provided UART device with the given configuration.
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2021-05-02 16:42:51 +10:00
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pub fn enable(
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mut device: D,
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2021-05-09 17:53:22 +10:00
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config: UartConfig,
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2021-05-02 16:42:51 +10:00
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frequency: Hertz,
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2021-05-09 17:53:22 +10:00
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) -> Result<UartPeripheral<Enabled, D>, Error> {
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2021-04-26 17:14:32 +10:00
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let effective_baudrate = configure_baudrate(&mut device, &config.baudrate, &frequency)?;
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2021-04-25 18:51:46 +10:00
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// Enable the UART, both TX and RX
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device.uartcr.write(|w| {
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w.uarten().set_bit();
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w.txe().set_bit();
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w.rxe().set_bit();
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w
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});
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device.uartlcr_h.write(|w| {
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w.fen().set_bit();
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set_format(w, &config.data_bits, &config.stop_bits, &config.parity);
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w
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});
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device.uartdmacr.write(|w| {
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w.txdmae().set_bit();
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w.rxdmae().set_bit();
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w
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});
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2021-05-09 17:53:22 +10:00
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Ok(UartPeripheral {
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device,
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config,
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effective_baudrate,
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_state: Enabled,
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2021-04-26 17:14:32 +10:00
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})
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2021-04-25 18:51:46 +10:00
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}
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}
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2021-05-09 17:53:22 +10:00
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impl<D: UartDevice> UartPeripheral<Enabled, D> {
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2021-04-25 18:51:46 +10:00
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/// Disable this UART Peripheral, falling back to the Disabled state.
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2021-05-09 17:53:22 +10:00
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pub fn disable(self) -> UartPeripheral<Disabled, D> {
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2021-04-26 04:25:29 +10:00
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// Disable the UART, both TX and RX
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self.device.uartcr.write(|w| {
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w.uarten().clear_bit();
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w.txe().clear_bit();
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w.rxe().clear_bit();
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w
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});
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2021-04-25 18:51:46 +10:00
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self.transition(Disabled)
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}
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2021-04-27 06:05:37 +10:00
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pub(crate) fn transmit_flushed(&self) -> nb::Result<(), Infallible> {
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if self.device.uartfr.read().txfe().bit_is_set() {
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Ok(())
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2021-05-02 16:42:51 +10:00
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} else {
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Err(WouldBlock)
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}
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}
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2021-04-25 18:51:46 +10:00
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fn uart_is_writable(&self) -> bool {
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self.device.uartfr.read().txff().bit_is_clear()
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}
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fn uart_is_readable(&self) -> bool {
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self.device.uartfr.read().rxfe().bit_is_clear()
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}
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/// Writes bytes to the UART.
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/// This function writes as long as it can. As soon that the FIFO is full, if :
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/// - 0 bytes were written, a WouldBlock Error is returned
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/// - some bytes were written, it is deemed to be a success
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2021-05-05 03:48:40 +10:00
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/// Upon success, the remaining slice is returned.
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2021-05-02 16:42:51 +10:00
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pub fn write_raw<'d>(&self, data: &'d [u8]) -> nb::Result<&'d [u8], Infallible> {
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let mut bytes_written = 0;
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for c in data {
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if !self.uart_is_writable() {
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if bytes_written == 0 {
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2021-05-02 16:42:51 +10:00
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return Err(WouldBlock);
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} else {
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return Ok(&data[bytes_written..]);
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2021-04-25 18:51:46 +10:00
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}
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}
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self.device.uartdr.write(|w| unsafe {
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w.data().bits(*c);
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w
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});
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2021-04-27 05:25:52 +10:00
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2021-04-26 04:00:56 +10:00
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bytes_written += 1;
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2021-04-25 18:51:46 +10:00
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}
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2021-05-05 16:06:47 +10:00
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Ok(&data[bytes_written..])
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2021-04-25 18:51:46 +10:00
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}
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/// Reads bytes from the UART.
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/// This function reads as long as it can. As soon that the FIFO is empty, if :
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/// - 0 bytes were read, a WouldBlock Error is returned
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/// - some bytes were read, it is deemed to be a success
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2021-05-05 03:48:40 +10:00
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/// Upon success, the remaining slice is returned.
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2021-05-02 16:27:29 +10:00
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pub fn read_raw<'b>(&self, buffer: &'b mut [u8]) -> nb::Result<&'b mut [u8], ReadError<'b>> {
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2021-04-25 18:51:46 +10:00
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let mut bytes_read = 0;
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Ok(loop {
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if !self.uart_is_readable() {
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if bytes_read == 0 {
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2021-05-02 16:42:51 +10:00
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return Err(WouldBlock);
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} else {
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break &mut buffer[bytes_read..];
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2021-04-25 18:51:46 +10:00
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}
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}
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if bytes_read < buffer.len() {
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2021-05-02 16:27:29 +10:00
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let mut error: Option<ReadErrorType> = None;
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if self.device.uartdr.read().oe().bit_is_set() {
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error = Some(ReadErrorType::Overrun);
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}
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if self.device.uartdr.read().be().bit_is_set() {
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error = Some(ReadErrorType::Break);
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}
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if self.device.uartdr.read().pe().bit_is_set() {
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error = Some(ReadErrorType::Parity);
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}
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if self.device.uartdr.read().fe().bit_is_set() {
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error = Some(ReadErrorType::Framing);
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}
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|
|
|
|
|
|
|
if let Some(err_type) = error {
|
|
|
|
return Err(Other(ReadError {
|
2021-05-02 16:42:51 +10:00
|
|
|
err_type,
|
|
|
|
discared: buffer,
|
2021-05-02 16:27:29 +10:00
|
|
|
}));
|
|
|
|
}
|
|
|
|
|
2021-04-25 18:51:46 +10:00
|
|
|
buffer[bytes_read] = self.device.uartdr.read().data().bits();
|
|
|
|
bytes_read += 1;
|
2021-05-02 16:42:51 +10:00
|
|
|
} else {
|
|
|
|
break &mut buffer[bytes_read..];
|
2021-04-25 18:51:46 +10:00
|
|
|
}
|
|
|
|
})
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Writes bytes to the UART.
|
|
|
|
/// This function blocks until the full buffer has been sent.
|
|
|
|
pub fn write_full_blocking(&self, data: &[u8]) {
|
2021-04-26 17:14:32 +10:00
|
|
|
let mut temp = data;
|
2021-04-25 18:51:46 +10:00
|
|
|
|
2021-04-26 17:14:32 +10:00
|
|
|
while !temp.is_empty() {
|
2021-04-27 06:05:37 +10:00
|
|
|
temp = match self.write_raw(temp) {
|
2021-04-26 17:14:32 +10:00
|
|
|
Ok(remaining) => remaining,
|
2021-04-25 18:51:46 +10:00
|
|
|
Err(WouldBlock) => continue,
|
2021-05-02 16:42:51 +10:00
|
|
|
Err(_) => unreachable!(),
|
2021-04-26 17:14:32 +10:00
|
|
|
}
|
2021-04-25 18:51:46 +10:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Reads bytes from the UART.
|
|
|
|
/// This function blocks until the full buffer has been received.
|
2021-05-02 17:04:05 +10:00
|
|
|
pub fn read_full_blocking(&self, buffer: &mut [u8]) -> Result<(), ReadErrorType> {
|
2021-04-25 18:51:46 +10:00
|
|
|
let mut offset = 0;
|
|
|
|
|
|
|
|
while offset != buffer.len() {
|
2021-04-27 06:05:37 +10:00
|
|
|
offset += match self.read_raw(&mut buffer[offset..]) {
|
2021-05-02 16:42:51 +10:00
|
|
|
Ok(remaining) => remaining.len(),
|
2021-05-02 17:04:05 +10:00
|
|
|
Err(e) => match e {
|
|
|
|
Other(inner) => return Err(inner.err_type),
|
|
|
|
WouldBlock => continue,
|
|
|
|
},
|
2021-04-26 17:14:32 +10:00
|
|
|
}
|
2021-04-25 18:51:46 +10:00
|
|
|
}
|
2021-05-02 17:04:05 +10:00
|
|
|
|
|
|
|
Ok(())
|
2021-04-25 18:51:46 +10:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-05 06:16:04 +10:00
|
|
|
/// The PL011 (PrimeCell UART) supports a fractional baud rate divider
|
|
|
|
/// From the wanted baudrate, we calculate the divider's two parts: integer and fractional parts.
|
|
|
|
/// Code inspired from the C SDK.
|
2021-05-02 16:42:51 +10:00
|
|
|
fn calculate_baudrate_dividers(
|
|
|
|
wanted_baudrate: &Baud,
|
|
|
|
frequency: &Hertz,
|
|
|
|
) -> Result<(u16, u16), Error> {
|
2021-05-05 16:02:53 +10:00
|
|
|
// See Chapter 4, Section 2 §7.1 from the datasheet for an explanation of how baudrate is
|
|
|
|
// calculated
|
2021-05-05 16:06:47 +10:00
|
|
|
let baudrate_div = frequency
|
|
|
|
.integer()
|
2021-05-05 03:54:15 +10:00
|
|
|
.checked_mul(8)
|
|
|
|
.and_then(|r| r.checked_div(*wanted_baudrate.integer()))
|
2021-05-02 16:42:51 +10:00
|
|
|
.ok_or(Error::BadArgument)?;
|
2021-04-25 18:51:46 +10:00
|
|
|
|
2021-04-26 17:14:32 +10:00
|
|
|
Ok(match (baudrate_div >> 7, ((baudrate_div & 0x7F) + 1) / 2) {
|
2021-04-25 18:51:46 +10:00
|
|
|
(0, _) => (1, 0),
|
|
|
|
|
2021-05-05 06:16:04 +10:00
|
|
|
(int_part, _) if int_part >= 65535 => (65535, 0),
|
2021-04-25 18:51:46 +10:00
|
|
|
|
2021-05-05 06:16:04 +10:00
|
|
|
(int_part, frac_part) => (int_part as u16, frac_part as u16),
|
2021-04-26 17:14:32 +10:00
|
|
|
})
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Baudrate configuration. Code loosely inspired from the C SDK.
|
2021-05-02 16:42:51 +10:00
|
|
|
fn configure_baudrate(
|
2021-05-09 17:53:22 +10:00
|
|
|
device: &mut dyn UartDevice,
|
2021-05-02 16:42:51 +10:00
|
|
|
wanted_baudrate: &Baud,
|
|
|
|
frequency: &Hertz,
|
|
|
|
) -> Result<Baud, Error> {
|
2021-05-05 06:16:04 +10:00
|
|
|
let (baud_div_int, baud_div_frac) = calculate_baudrate_dividers(wanted_baudrate, frequency)?;
|
2021-04-25 18:51:46 +10:00
|
|
|
|
2021-05-05 06:16:04 +10:00
|
|
|
// First we load the integer part of the divider.
|
2021-04-25 18:51:46 +10:00
|
|
|
device.uartibrd.write(|w| unsafe {
|
2021-05-05 06:16:04 +10:00
|
|
|
w.baud_divint().bits(baud_div_int as u16);
|
2021-04-25 18:51:46 +10:00
|
|
|
w
|
|
|
|
});
|
2021-05-05 06:16:04 +10:00
|
|
|
|
|
|
|
// Then we load the fractional part of the divider.
|
2021-04-25 18:51:46 +10:00
|
|
|
device.uartfbrd.write(|w| unsafe {
|
2021-05-05 06:16:04 +10:00
|
|
|
w.baud_divfrac().bits(baud_div_frac as u8);
|
2021-04-25 18:51:46 +10:00
|
|
|
w
|
|
|
|
});
|
|
|
|
|
|
|
|
// PL011 needs a (dummy) line control register write to latch in the
|
|
|
|
// divisors. We don't want to actually change LCR contents here.
|
2021-05-02 16:42:51 +10:00
|
|
|
device.uartlcr_h.modify(|_, w| w);
|
2021-04-25 18:51:46 +10:00
|
|
|
|
2021-05-02 16:42:51 +10:00
|
|
|
Ok(Baud(
|
2021-05-05 06:16:04 +10:00
|
|
|
(4 * *frequency.integer()) / (64 * baud_div_int + baud_div_frac) as u32,
|
2021-05-02 16:42:51 +10:00
|
|
|
))
|
2021-04-25 18:51:46 +10:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Format configuration. Code loosely inspired from the C SDK.
|
2021-05-02 16:42:51 +10:00
|
|
|
fn set_format<'w>(
|
|
|
|
w: &'w mut UART_LCR_H_Writer,
|
|
|
|
data_bits: &DataBits,
|
|
|
|
stop_bits: &StopBits,
|
|
|
|
parity: &Option<Parity>,
|
|
|
|
) -> &'w mut UART_LCR_H_Writer {
|
2021-04-25 18:51:46 +10:00
|
|
|
match parity {
|
|
|
|
Some(p) => {
|
|
|
|
w.pen().set_bit();
|
|
|
|
match p {
|
2021-05-05 03:56:36 +10:00
|
|
|
Parity::Odd => w.eps().clear_bit(),
|
2021-05-02 16:42:51 +10:00
|
|
|
Parity::Even => w.eps().set_bit(),
|
2021-04-25 18:51:46 +10:00
|
|
|
};
|
2021-05-02 16:42:51 +10:00
|
|
|
}
|
|
|
|
None => {
|
|
|
|
w.pen().bit(false);
|
|
|
|
}
|
2021-04-25 18:51:46 +10:00
|
|
|
};
|
|
|
|
|
2021-05-02 16:42:51 +10:00
|
|
|
unsafe {
|
|
|
|
w.wlen().bits(match data_bits {
|
|
|
|
DataBits::Five => 0b00,
|
|
|
|
DataBits::Six => 0b01,
|
|
|
|
DataBits::Seven => 0b10,
|
|
|
|
DataBits::Eight => 0b11,
|
|
|
|
})
|
2021-04-25 18:51:46 +10:00
|
|
|
};
|
|
|
|
|
|
|
|
match stop_bits {
|
2021-05-05 03:56:36 +10:00
|
|
|
StopBits::One => w.stp2().clear_bit(),
|
2021-05-02 16:42:51 +10:00
|
|
|
StopBits::Two => w.stp2().set_bit(),
|
2021-04-25 18:51:46 +10:00
|
|
|
};
|
|
|
|
|
|
|
|
w
|
|
|
|
}
|
2021-05-02 16:41:20 +10:00
|
|
|
|
2021-05-09 17:53:22 +10:00
|
|
|
impl<D: UartDevice> Read<u8> for UartPeripheral<Enabled, D> {
|
2021-05-02 17:04:05 +10:00
|
|
|
type Error = ReadErrorType;
|
2021-05-02 16:41:20 +10:00
|
|
|
|
|
|
|
fn read(&mut self) -> nb::Result<u8, Self::Error> {
|
|
|
|
let byte: &mut [u8] = &mut [0; 1];
|
|
|
|
|
2021-05-02 17:04:05 +10:00
|
|
|
match self.read_raw(byte) {
|
|
|
|
Ok(_) => Ok(byte[0]),
|
|
|
|
Err(e) => match e {
|
2021-05-05 16:06:47 +10:00
|
|
|
Other(inner) => Err(Other(inner.err_type)),
|
|
|
|
WouldBlock => Err(WouldBlock),
|
2021-05-02 17:04:05 +10:00
|
|
|
},
|
2021-05-02 16:41:20 +10:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-09 17:53:22 +10:00
|
|
|
impl<D: UartDevice> Write<u8> for UartPeripheral<Enabled, D> {
|
2021-05-02 16:41:20 +10:00
|
|
|
type Error = Infallible;
|
|
|
|
|
|
|
|
fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
|
2021-05-05 16:06:47 +10:00
|
|
|
if self.write_raw(&[word]).is_err() {
|
2021-05-02 16:41:20 +10:00
|
|
|
Err(WouldBlock)
|
2021-05-02 16:42:51 +10:00
|
|
|
} else {
|
2021-05-02 16:41:20 +10:00
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn flush(&mut self) -> nb::Result<(), Self::Error> {
|
|
|
|
self.transmit_flushed()
|
|
|
|
}
|
|
|
|
}
|