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Fix some clippy warnings flagged by current beta (#505)
* Fix some clippy warnings flagged by current beta (One warning was just silenced because I consider the current code more readable) * cargo fmt
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d1377acc19
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@ -270,15 +270,7 @@ impl PicoExplorer {
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pub fn get_adc<Pin: Channel<Adc, ID = u8>>(&mut self, channel: &mut Pin) -> f32 {
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// scale raw 12-bit adc value to 0 .. 1 float
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let adc_value: u16 = self.adc.read(channel).unwrap();
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let mut result: f32 = f32::from(adc_value) / f32::from(1u16 << 12);
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// clamp result to 0 .. 1
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if result > 1.0 {
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result = 1.0
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}
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if result < 0.0 {
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result = 0.0
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}
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result
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let result: f32 = f32::from(adc_value) / f32::from(1u16 << 12);
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result.clamp(0.0, 1.0)
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}
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}
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@ -8,7 +8,6 @@ mod app {
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use embedded_hal::digital::v2::OutputPin;
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use fugit::ExtU64;
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use fugit::MicrosDurationU32;
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use rp_pico::{
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hal::{
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self,
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@ -20,8 +19,6 @@ mod app {
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XOSC_CRYSTAL_FREQ,
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};
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const SCAN_TIME_US: MicrosDurationU32 = MicrosDurationU32::secs(1);
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#[shared]
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struct Shared {
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led: hal::gpio::Pin<hal::gpio::pin::bank0::Gpio25, hal::gpio::PushPullOutput>,
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@ -216,7 +216,7 @@ impl<P: PIOExt> PIO<P> {
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});
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self.used_instruction_space |= Self::instruction_mask(p.code.len()) << offset;
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Ok(InstalledProgram {
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offset: offset as u8,
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offset,
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length: p.code.len() as u8,
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side_set: p.side_set,
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wrap: p.wrap,
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@ -2028,9 +2028,8 @@ impl<P: PIOExt> PIOBuilder<P> {
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w.out_sticky().bit(self.out_sticky);
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w.wrap_top().bits(offset as u8 + self.program.wrap.source);
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w.wrap_bottom()
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.bits(offset as u8 + self.program.wrap.target);
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w.wrap_top().bits(offset + self.program.wrap.source);
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w.wrap_bottom().bits(offset + self.program.wrap.target);
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let n = match self.mov_status {
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MovStatusConfig::Tx(n) => {
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@ -2085,7 +2084,7 @@ impl<P: PIOExt> PIOBuilder<P> {
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// to the beginning of the program we loaded in.
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let instr = InstructionOperands::JMP {
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condition: pio::JmpCondition::Always,
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address: offset as u8,
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address: offset,
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}
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.encode();
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// Safety: Only instance owning the SM
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@ -157,7 +157,7 @@ impl SioFifo {
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// Write the value to the FIFO - the other core will now be able to
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// pop it off its end of the FIFO.
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self.write(value as u32);
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self.write(value);
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// Fire off an event to the other core
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cortex_m::asm::sev();
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@ -158,7 +158,7 @@ impl<D: SpiDevice, const DS: u8> Spi<Disabled, D, DS> {
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self.device.reset_bring_up(resets);
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self.set_baudrate(peri_frequency, baudrate);
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self.set_format(DS as u8, mode);
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self.set_format(DS, mode);
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// Always enable DREQ signals -- harmless if DMA is not listening
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self.device
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.sspdmacr
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@ -280,7 +280,7 @@ fn configure_baudrate(
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// First we load the integer part of the divider.
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device.uartibrd.write(|w| unsafe {
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w.baud_divint().bits(baud_div_int as u16);
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w.baud_divint().bits(baud_div_int);
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w
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});
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@ -124,6 +124,7 @@ use usb_device::{
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#[cfg(feature = "rp2040-e5")]
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mod errata5;
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#[allow(clippy::bool_to_int_with_if)]
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fn ep_addr_to_ep_buf_ctrl_idx(ep_addr: EndpointAddress) -> usize {
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ep_addr.index() * 2 + (if ep_addr.is_in() { 0 } else { 1 })
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}
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