From 07c183a63650982a86a1bbfdf1383d682630e186 Mon Sep 17 00:00:00 2001 From: "Jonathan Pallant (42 Technology)" Date: Mon, 27 Sep 2021 17:29:50 +0100 Subject: [PATCH] Remove hard coded clock speed from ADC example. --- rp2040-hal/examples/adc.rs | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/rp2040-hal/examples/adc.rs b/rp2040-hal/examples/adc.rs index e98accc..53f3257 100644 --- a/rp2040-hal/examples/adc.rs +++ b/rp2040-hal/examples/adc.rs @@ -20,18 +20,18 @@ use panic_halt as _; // Alias for our HAL crate use rp2040_hal as hal; -// An ADC trait we need -use embedded_hal::adc::OneShot; - -// A debug/string formatting trait we need +// The traits we need use core::fmt::Write; +use embedded_hal::adc::OneShot; +use embedded_time::fixed_point::FixedPoint; +use rp2040_hal::clocks::Clock; // A shorter alias for the Peripheral Access Crate, which provides low-level // register access use hal::pac; -// The linker will place this boot block at the start of our program image. We -// need this to help the ROM bootloader get our code up and running. +/// The linker will place this boot block at the start of our program image. We +/// need this to help the ROM bootloader get our code up and running. #[link_section = ".boot2"] #[used] pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER; @@ -40,9 +40,6 @@ pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER; /// if your board has a different frequency const XTAL_FREQ_HZ: u32 = 12_000_000u32; -/// Run RP2040 at 125 MHz -const SYS_FREQ_HZ: u32 = hal::pll::common_configs::PLL_SYS_125MHZ.vco_freq.0; - /// Entry point to our bare-metal application. /// /// The `#[entry]` macro ensures the Cortex-M start-up code calls this function @@ -74,7 +71,7 @@ fn main() -> ! { // The delay object lets us wait for specified amounts of time (in // milliseconds) - let mut delay = cortex_m::delay::Delay::new(core.SYST, SYS_FREQ_HZ); + let mut delay = cortex_m::delay::Delay::new(core.SYST, clocks.system_clock.freq().integer()); // The single-cycle I/O block controls our GPIO pins let sio = hal::sio::Sio::new(pac.SIO);