From 25e477b73e1399f47a7444cefc26605037804dd1 Mon Sep 17 00:00:00 2001
From: Henrik Lievonen <henrik.lievonen@hotmail.com>
Date: Mon, 20 Sep 2021 05:20:42 +0300
Subject: [PATCH] Fix PWM set/clr_inverted (#122)

---
 rp2040-hal/src/pwm/mod.rs | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/rp2040-hal/src/pwm/mod.rs b/rp2040-hal/src/pwm/mod.rs
index 2282bc8..d0ae990 100644
--- a/rp2040-hal/src/pwm/mod.rs
+++ b/rp2040-hal/src/pwm/mod.rs
@@ -520,18 +520,6 @@ impl<S: SliceId, M: SliceMode, C: ChannelId> Channel<S, M, C> {
             duty_cycle,
         }
     }
-
-    /// Invert channel output
-    #[inline]
-    pub fn set_inverted(&mut self) {
-        self.regs.write_inv_b(true)
-    }
-
-    /// Invert channel output or not
-    #[inline]
-    pub fn clr_inverted(&mut self) {
-        self.regs.write_inv_b(false)
-    }
 }
 
 impl<S: SliceId, M: SliceMode, C: ChannelId> Sealed for Channel<S, M, C> {}
@@ -603,6 +591,18 @@ impl<S: SliceId, M: SliceMode + ValidSliceMode<S>> Channel<S, M, A> {
             pin: pin.into_mode(),
         }
     }
+
+    /// Invert channel output
+    #[inline]
+    pub fn set_inverted(&mut self) {
+        self.regs.write_inv_a(true)
+    }
+
+    /// Stop inverting channel output
+    #[inline]
+    pub fn clr_inverted(&mut self) {
+        self.regs.write_inv_a(false)
+    }
 }
 
 impl<S: SliceId, M: SliceMode + ValidSliceMode<S>> Channel<S, M, B> {
@@ -618,6 +618,18 @@ impl<S: SliceId, M: SliceMode + ValidSliceMode<S>> Channel<S, M, B> {
             pin: pin.into_mode(),
         }
     }
+
+    /// Invert channel output
+    #[inline]
+    pub fn set_inverted(&mut self) {
+        self.regs.write_inv_b(true)
+    }
+
+    /// Stop inverting channel output
+    #[inline]
+    pub fn clr_inverted(&mut self) {
+        self.regs.write_inv_b(false)
+    }
 }
 
 impl<S: SliceId, M: SliceMode + ValidSliceInputMode<S>> Channel<S, M, B> {