mirror of
https://github.com/italicsjenga/rp-hal-boards.git
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Add support for the Interpolator (#371)
* Implementation of the interpolator. * corrected formatting * fixed documentation code * add clamp flag to LaneCtrl * addition of an example for the interpolator * put documentation behind /// * rewording comment for clarity * using more idiomatic fn new
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Kasil
GitHub
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441
boards/rp-pico/examples/pico_interpolator.rs
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441
boards/rp-pico/examples/pico_interpolator.rs
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@ -0,0 +1,441 @@
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//! # Pico Interpolator Example
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//!
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//! Example demonstrating the usage of the hardware interpolator.
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//!
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//! Runs several test programs, outputs the result on LEDs.
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//! Green led for successful test connects to GPIO3.
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//! Red led for unsuccessful test connects to GPIO4.
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//! In case of failure, the system LED blinks the number of the test.
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//! In case of success, the system LED stays lit.
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//!
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//! See the `Cargo.toml` file for Copyright and license details.
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#![no_std]
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#![no_main]
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// The macro for our start-up function
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use rp_pico::entry;
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// Time handling traits
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use embedded_time::rate::*;
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// GPIO traits
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use embedded_hal::digital::v2::OutputPin;
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// Ensure we halt the program on panic (if we don't mention this crate it won't
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// be linked)
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use panic_halt as _;
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// A shorter alias for the Peripheral Access Crate, which provides low-level
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// register access
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use rp_pico::hal::pac;
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// A shorter alias for the Hardware Abstraction Layer, which provides
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// higher-level drivers.
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use rp_pico::hal;
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// Pull in any important traits
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use rp_pico::hal::prelude::*;
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use rp_pico::hal::sio::{Interp, Interp0, Interp1, Lane, LaneCtrl};
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/// Entry point to our bare-metal application.
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///
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/// The `#[entry]` macro ensures the Cortex-M start-up code calls this function
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/// as soon as all global variables are initialised.
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///
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/// The function configures the RP2040 peripherals, then just reads the button
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/// and sets the LED appropriately.
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#[entry]
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fn main() -> ! {
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// Grab our singleton objects
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let mut pac = pac::Peripherals::take().unwrap();
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let core = pac::CorePeripherals::take().unwrap();
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// Set up the watchdog driver - needed by the clock setup code
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let mut watchdog = hal::Watchdog::new(pac.WATCHDOG);
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// Configure the clocks
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//
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// The default is to generate a 125 MHz system clock
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let clocks = hal::clocks::init_clocks_and_plls(
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rp_pico::XOSC_CRYSTAL_FREQ,
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pac.XOSC,
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pac.CLOCKS,
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pac.PLL_SYS,
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pac.PLL_USB,
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&mut pac.RESETS,
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&mut watchdog,
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)
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.ok()
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.unwrap();
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// The delay object lets us wait for specified amounts of time (in
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// milliseconds)
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let mut delay = cortex_m::delay::Delay::new(core.SYST, clocks.system_clock.freq().integer());
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// The single-cycle I/O block controls our GPIO pins
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let mut sio = hal::Sio::new(pac.SIO);
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// Set the pins up according to their function on this particular board
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let pins = rp_pico::Pins::new(
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pac.IO_BANK0,
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pac.PADS_BANK0,
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sio.gpio_bank0,
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&mut pac.RESETS,
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);
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// Our LED outputs
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let mut system_led_pin = pins.led.into_push_pull_output();
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let mut green_led_pin = pins.gpio3.into_push_pull_output();
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let mut red_led_pin = pins.gpio4.into_push_pull_output();
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system_led_pin.set_low().unwrap();
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green_led_pin.set_low().unwrap();
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red_led_pin.set_low().unwrap();
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let mut choose_led = |index: u32, result: bool| {
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if result {
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// blink the green led once to indicate success
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green_led_pin.set_high().unwrap();
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delay.delay_ms(500);
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green_led_pin.set_low().unwrap();
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delay.delay_ms(500);
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} else {
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// turn the red led on to indicate failure
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// and blink the on board led to indicate which test failed, looping forever
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red_led_pin.set_high().unwrap();
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loop {
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for _ in 0..index {
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system_led_pin.set_high().unwrap();
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delay.delay_ms(200);
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system_led_pin.set_low().unwrap();
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delay.delay_ms(200);
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}
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delay.delay_ms(1000);
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}
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}
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};
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// Run forever, setting the LED according to the button
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choose_led(1, multiplication_table(&mut sio.interp0));
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choose_led(2, moving_mask(&mut sio.interp0));
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choose_led(3, cross_lanes(&mut sio.interp0));
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choose_led(4, simple_blend1(&mut sio.interp0));
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choose_led(5, simple_blend2(&mut sio.interp0));
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choose_led(6, clamp(&mut sio.interp1));
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choose_led(7, texture_mapping(&mut sio.interp0));
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// turn the on board led on to indicate testing is done
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system_led_pin.set_high().unwrap();
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loop {
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delay.delay_ms(1000);
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}
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}
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fn multiplication_table(interp: &mut Interp0) -> bool {
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//get the default configuration that just keep adding base into accum
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let config = LaneCtrl::new();
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//write the configuration to the hardware.
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interp.get_lane0().set_ctrl(config.encode());
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//set the accumulator to 0 and the base to 9
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interp.get_lane0().set_accum(0);
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interp.get_lane0().set_base(9);
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//the expected output for comparison
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let expected = [9, 18, 27, 36, 45, 54, 63, 72, 81, 90];
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for i in expected {
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//returns the value of accum + base and sets accum to the same value
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let value = interp.get_lane0().pop();
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if value != i {
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return false; //inform that the interpolator did not return the expected value
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}
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}
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true
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}
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fn moving_mask(interp: &mut Interp0) -> bool {
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//get the default configuration that just keep adding base into accum
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let mut config = LaneCtrl::new();
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interp.get_lane0().set_accum(0x1234ABCD);
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let expected = [
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0x0000_000D,
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0x0000_00C0,
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0x0000_0B00,
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0x0000_A000,
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0x0004_0000,
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0x0030_0000,
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0x0200_0000,
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0x1000_0000,
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];
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for i in 0..8 {
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// LSB, then MSB. These are inclusive, so 0,31 means "the entire 32 bit register"
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config.mask_lsb = i * 4;
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config.mask_msb = i * 4 + 3;
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interp.get_lane0().set_ctrl(config.encode());
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// Reading read_raw() returns the lane data
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// after shifting, masking and sign extending, without adding base
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if interp.get_lane0().read_raw() != expected[i as usize] {
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return false;
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}
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}
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let signed_expected = [
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0xFFFF_FFFD,
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0xFFFF_FFC0,
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0xFFFF_FB00,
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0xFFFF_A000,
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0x0004_0000,
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0x0030_0000,
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0x0200_0000,
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0x1000_0000,
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];
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config.signed = true;
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for i in 0..8 {
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config.mask_lsb = i * 4;
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config.mask_msb = i * 4 + 3;
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interp.get_lane0().set_ctrl(config.encode());
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if interp.get_lane0().read_raw() != signed_expected[i as usize] {
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return false;
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}
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}
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true
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}
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fn cross_lanes(interp: &mut Interp0) -> bool {
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// this configuration will at the time of pop()
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// when applied to lane0 : set lane0 accumulator to the result from lane1
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// when applied to lane1 : set lane1 accumulator to the result from lane0
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let config = LaneCtrl {
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cross_result: true,
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..LaneCtrl::new()
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};
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let encoded_config = config.encode();
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// each lane is used through an accessor,
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// as lanes mutate each other, they can not be borrowed at the same time
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interp.get_lane0().set_ctrl(encoded_config);
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interp.get_lane1().set_ctrl(encoded_config);
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interp.get_lane0().set_accum(123);
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interp.get_lane1().set_accum(456);
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// lane0 will add 1 to its result, lane1 will add nothing
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interp.get_lane0().set_base(1);
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interp.get_lane1().set_base(0);
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let expected = [
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(124, 456),
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(457, 124),
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(125, 457),
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(458, 125),
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(126, 458),
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(459, 126),
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(127, 459),
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(460, 127),
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(128, 460),
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(461, 128),
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];
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for i in expected {
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if i != (interp.get_lane0().peek(), interp.get_lane1().pop()) {
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return false;
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}
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}
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true
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}
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fn simple_blend1(interp: &mut Interp0) -> bool {
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let config = LaneCtrl {
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blend: true,
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..LaneCtrl::new()
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};
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//enable blend mode
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interp.get_lane0().set_ctrl(config.encode());
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//make sure the default configuration is in lane1 as the value may be shifted and masked.
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interp.get_lane1().set_ctrl(LaneCtrl::new().encode());
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//set the minimum value for interp.get_lane0().set_accum(0) 0/256
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interp.get_lane0().set_base(500);
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//set the maximum value which is inaccessible
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// as the blend is done between 0/256 and 255/256
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interp.get_lane1().set_base(1000);
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let expected = [500, 582, 666, 748, 832, 914, 998];
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for i in 0..=6 {
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interp.get_lane1().set_accum(255 * i / 6);
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if expected[i as usize] != interp.get_lane1().peek() {
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return false;
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}
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}
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true
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}
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fn simple_blend2(interp: &mut Interp0) -> bool {
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let config = LaneCtrl {
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blend: true,
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..LaneCtrl::new()
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};
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//enable blend mode
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interp.get_lane0().set_ctrl(config.encode());
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interp.get_lane0().set_base((-1000i32) as u32);
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interp.get_lane1().set_base(1000);
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let mut config1 = LaneCtrl {
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signed: true,
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..LaneCtrl::new()
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};
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interp.get_lane1().set_ctrl(config1.encode());
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let expected_signed = [-1000, -672, -336, -8, 328, 656, 992];
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for i in 0..=6 {
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// write a value between 0 and 256 (exclusive)
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interp.get_lane1().set_accum(255 * i / 6);
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// reads it as a value between -1000 and 1000 (exclusive)
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if interp.get_lane1().peek() as i32 != expected_signed[i as usize] {
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return false;
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}
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}
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config1.signed = false;
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interp.get_lane1().set_ctrl(config1.encode());
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let expected_unsigned = [
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0xfffffc18, 0xd5fffd60, 0xaafffeb0, 0x80fffff8, 0x56000148, 0x2c000290, 0x010003e0,
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];
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for i in 0..=6 {
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interp.get_lane1().set_accum(255 * i / 6);
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// reads a value between 4294966296 and 1000
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if interp.get_lane1().peek() != expected_unsigned[i as usize] {
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return false;
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}
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}
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true
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}
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///Divides by 4 and clamp the value between 0 and 255 inclusive
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fn clamp(interp: &mut Interp1) -> bool {
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// Enables Clamp ONLY AVAILABLE ON Interp1
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// shift two bits to the right and mask the two most significant bits
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// because sign extension is made after the mask
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let config = LaneCtrl {
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clamp: true,
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shift: 2,
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mask_lsb: 0,
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mask_msb: 29,
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signed: true,
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..LaneCtrl::new()
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};
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interp.get_lane0().set_ctrl(config.encode());
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//set minimum value of result
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interp.get_lane0().set_base(0);
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//set maximum value of result
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interp.get_lane1().set_base(255);
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let values: [(i32, i32); 9] = [
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(-1024, 0),
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(-768, 0),
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(-512, 0),
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(-256, 0),
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(0, 0),
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(256, 64),
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(512, 128),
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(768, 192),
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(1024, 255),
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];
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for (arg, result) in values {
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interp.get_lane0().set_accum(arg as u32);
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if result != interp.get_lane0().peek() as i32 {
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return false;
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}
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}
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true
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}
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fn texture_mapping(interp: &mut Interp0) -> bool {
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#[rustfmt::skip]
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let texture: [u8;16] = [
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0x00, 0x01, 0x02, 0x03,
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0x10, 0x11, 0x12, 0x13,
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0x20, 0x21, 0x22, 0x23,
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0x30, 0x31, 0x32, 0x33,
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];
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// the position will be given in fixed point with 16 bits
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// fractional part
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let uv_fractional_bits = 16;
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let texture_width_bits = 2;
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let texture_height_bits = 2;
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// bits
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// 3322222222221111 1111110000000000
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// 1098765432109876 5432109876543210
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// accum0 u axis coordinate xx xxxxxxxxxxxxxxxx 18 bits
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// after shift and mask xx
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// accum1 v axis xx xxxxxxxxxxxxxxxx 18 bits
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// after shift and mask xx
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// add_raw make the interpolator increment the accumulator
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// with the base value without masking or shifting
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let config0 = LaneCtrl {
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add_raw: true,
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shift: uv_fractional_bits,
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mask_lsb: 0,
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mask_msb: texture_width_bits - 1,
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..LaneCtrl::new()
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};
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interp.get_lane0().set_ctrl(config0.encode());
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let config1 = LaneCtrl {
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add_raw: true,
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shift: uv_fractional_bits - texture_width_bits,
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mask_lsb: texture_width_bits,
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mask_msb: texture_width_bits + texture_height_bits - 1,
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..LaneCtrl::new()
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};
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interp.get_lane1().set_ctrl(config1.encode());
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interp.set_base(0);
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// set starting position to 0x0
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// will move 1/2 a pixel horizontally
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// and 1/3 a pixel vertically per call to pop()
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interp.get_lane0().set_accum(0);
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interp.get_lane0().set_base(65536 / 2);
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interp.get_lane1().set_accum(0);
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interp.get_lane1().set_base(65536 / 3);
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let expected = [
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0x00, 0x00, 0x01, 0x01, 0x12, 0x12, 0x13, 0x23, 0x20, 0x20, 0x31, 0x31,
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];
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for i in expected {
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if i != texture[interp.pop() as usize] {
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return false;
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}
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}
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// reset the starting position
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interp.get_lane0().set_accum(0);
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interp.get_lane1().set_accum(0);
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interp.set_base(texture.as_ptr() as u32);
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for i in expected {
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// This is unsafe and should be done extremely carefully
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// remember to follow memory alignment,
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// reading or writing an unaligned address will crash
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if i != unsafe { *(interp.pop() as *const u8) } {
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return false;
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}
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}
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true
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}
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// End of file
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@ -60,9 +60,10 @@ pub struct Sio {
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pub hwdivider: HwDivider,
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/// Inter-core FIFO
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pub fifo: SioFifo,
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// we can hand out other things here, for example:
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// interp0
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// interp1
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/// Interpolator 0
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pub interp0: Interp0,
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/// Interpolator 1
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pub interp1: Interp1,
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}
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impl Sio {
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@ -74,6 +75,14 @@ impl Sio {
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gpio_qspi: SioGpioQspi { _private: () },
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fifo: SioFifo { _private: () },
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hwdivider: HwDivider { _private: () },
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interp0: Interp0 {
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lane0: Interp0Lane0 { _private: () },
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lane1: Interp0Lane1 { _private: () },
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},
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interp1: Interp1 {
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lane0: Interp1Lane0 { _private: () },
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lane1: Interp1Lane1 { _private: () },
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},
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}
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}
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|
|
@ -667,3 +676,239 @@ pub unsafe fn spinlock_reset() {
|
|||
SPINLOCK0_PTR.wrapping_add(i).write_volatile(1);
|
||||
}
|
||||
}
|
||||
|
||||
/// Configuration struct for one lane of the interpolator
|
||||
pub struct LaneCtrl {
|
||||
/// Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled:
|
||||
/// - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of
|
||||
/// BASE0 and an upper bound of BASE1.
|
||||
/// - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED
|
||||
pub clamp: bool,
|
||||
/// Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled:
|
||||
/// - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled
|
||||
/// by the 8 LSBs of lane 1 shift and mask value (a fractional number between
|
||||
/// 0 and 255/256ths)
|
||||
/// - LANE0 result does not have BASE0 added (yields only
|
||||
/// the 8 LSBs of lane 1 shift+mask value)
|
||||
/// - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)
|
||||
/// LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.
|
||||
pub blend: bool,
|
||||
/// Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus.
|
||||
/// No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
|
||||
/// of pointers into flash or SRAM.
|
||||
pub force_msb: u8,
|
||||
/// Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
|
||||
pub add_raw: bool,
|
||||
/// Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP.
|
||||
pub cross_result: bool,
|
||||
/// Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.
|
||||
/// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
|
||||
pub cross_input: bool,
|
||||
/// Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
|
||||
/// before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
|
||||
pub signed: bool,
|
||||
/// Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive)
|
||||
/// Setting MSB < LSB may cause chip to turn inside-out
|
||||
pub mask_msb: u8,
|
||||
/// Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)
|
||||
pub mask_lsb: u8,
|
||||
/// Bits 0:4 - Logical right-shift applied to accumulator before masking
|
||||
pub shift: u8,
|
||||
}
|
||||
|
||||
impl LaneCtrl {
|
||||
/// Default configuration. Normal operation, unsigned, mask keeps all bits, no shift.
|
||||
pub const fn new() -> Self {
|
||||
Self {
|
||||
clamp: false,
|
||||
blend: false,
|
||||
force_msb: 0,
|
||||
add_raw: false,
|
||||
cross_result: false,
|
||||
cross_input: false,
|
||||
signed: false,
|
||||
mask_msb: 31,
|
||||
mask_lsb: 0,
|
||||
shift: 0,
|
||||
}
|
||||
}
|
||||
|
||||
/// encode the configuration to be loaded in the ctrl register of one lane of an interpolator
|
||||
pub const fn encode(&self) -> u32 {
|
||||
assert!(!(self.blend && self.clamp));
|
||||
assert!(self.force_msb < 0b100);
|
||||
assert!(self.mask_msb < 0b100000);
|
||||
assert!(self.mask_lsb < 0b100000);
|
||||
assert!(self.mask_msb >= self.mask_lsb);
|
||||
assert!(self.shift < 0b100000);
|
||||
((self.clamp as u32) << 22)
|
||||
| ((self.blend as u32) << 21)
|
||||
| ((self.force_msb as u32) << 19)
|
||||
| ((self.add_raw as u32) << 18)
|
||||
| ((self.cross_result as u32) << 17)
|
||||
| ((self.cross_input as u32) << 16)
|
||||
| ((self.signed as u32) << 15)
|
||||
| ((self.mask_msb as u32) << 10)
|
||||
| ((self.mask_lsb as u32) << 5)
|
||||
| (self.shift as u32)
|
||||
}
|
||||
}
|
||||
|
||||
///Trait representing the functionnality of a single lane of an interpolator.
|
||||
pub trait Lane {
|
||||
///Read the lane result, and simultaneously write lane results to both accumulators.
|
||||
fn pop(&mut self) -> u32;
|
||||
///Read the lane result without altering any internal state
|
||||
fn peek(&self) -> u32;
|
||||
///Write a value to the accumulator
|
||||
fn set_accum(&mut self, v: u32);
|
||||
///Read the value from the accumulator
|
||||
fn get_accum(&self) -> u32;
|
||||
///Write a value to the base register
|
||||
fn set_base(&mut self, v: u32);
|
||||
///Read the value from the base register
|
||||
fn get_base(&self) -> u32;
|
||||
///Write to the control register
|
||||
fn set_ctrl(&mut self, v: u32);
|
||||
///Read from the control register
|
||||
fn get_ctrl(&self) -> u32;
|
||||
///Add the value to the accumulator register
|
||||
fn add_accum(&mut self, v: u32);
|
||||
///Read the raw shift and mask value (BASE register not added)
|
||||
fn read_raw(&self) -> u32;
|
||||
}
|
||||
|
||||
///Trait representing the functionnality of an interpolator.
|
||||
/// ```no_run
|
||||
/// use rp2040_hal::sio::{Sio,LaneCtrl,Lane};
|
||||
/// use rp2040_hal::pac;
|
||||
/// let mut peripherals = pac::Peripherals::take().unwrap();
|
||||
/// let mut sio = Sio::new(peripherals.SIO);
|
||||
///
|
||||
/// // by having the configuration const, the validity is checked during compilation.
|
||||
/// const config: u32 = LaneCtrl {
|
||||
/// mask_msb: 4, // Most significant bit of the mask is bit 4
|
||||
/// // By default the least significant bit is bit 0
|
||||
/// // this will keep only the 5 least significant bits.
|
||||
/// // this is equivalent to %32
|
||||
/// ..LaneCtrl::new()
|
||||
/// }.encode();
|
||||
/// sio.interp0.get_lane0().set_ctrl(config);
|
||||
/// sio.interp0.get_lane0().set_accum(0);
|
||||
/// sio.interp0.get_lane0().set_base(1); // will increment the value by 1 on each call to pop
|
||||
///
|
||||
/// sio.interp0.get_lane0().peek(); // returns 1
|
||||
/// sio.interp0.get_lane0().pop(); // returns 1
|
||||
/// sio.interp0.get_lane0().pop(); // returns 2
|
||||
/// sio.interp0.get_lane0().pop(); // returns 3
|
||||
/// ```
|
||||
pub trait Interp {
|
||||
///Read the interpolator result (Result 2 in the datasheet), and simultaneously write lane results to both accumulators.
|
||||
fn pop(&mut self) -> u32;
|
||||
///Read the interpolator result (Result 2 in the datasheet) without altering any internal state
|
||||
fn peek(&self) -> u32;
|
||||
///Write to the interpolator Base register (Base2 in the datasheet)
|
||||
fn set_base(&mut self, v: u32);
|
||||
///Read the interpolator Base register (Base2 in the datasheet)
|
||||
fn get_base(&self) -> u32;
|
||||
}
|
||||
|
||||
macro_rules! interpolators {
|
||||
(
|
||||
$($interp:ident : ( $( [ $lane:ident,$lane_id:expr ] ),+ ) ),+
|
||||
) => {
|
||||
$crate::paste::paste! {
|
||||
|
||||
|
||||
$(
|
||||
$(
|
||||
#[doc = "The lane " $lane_id " of " $interp]
|
||||
pub struct [<$interp $lane>]{
|
||||
_private: (),
|
||||
}
|
||||
impl Lane for [<$interp $lane>]{
|
||||
fn pop(&mut self) ->u32{
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _pop_ $lane:lower>].read().bits()
|
||||
}
|
||||
fn peek(&self) ->u32{
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _peek_ $lane:lower>].read().bits()
|
||||
}
|
||||
fn set_accum(&mut self,v:u32){
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _accum $lane_id>].write(|w| unsafe { w.bits(v) });
|
||||
}
|
||||
fn get_accum(&self)->u32{
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _accum $lane_id>].read().bits()
|
||||
}
|
||||
fn set_base(&mut self, v:u32){
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _base $lane_id>].write(|w| unsafe { w.bits(v) });
|
||||
}
|
||||
fn get_base(&self)->u32{
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _base $lane_id>].read().bits()
|
||||
}
|
||||
fn set_ctrl(&mut self, v:u32){
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _ctrl_lane $lane_id>].write(|w| unsafe { w.bits(v) });
|
||||
}
|
||||
fn get_ctrl(&self)->u32{
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _ctrl_lane $lane_id>].read().bits()
|
||||
}
|
||||
fn add_accum(&mut self, v:u32){
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _accum $lane_id _add>].write(|w| unsafe { w.bits(v) });
|
||||
}
|
||||
fn read_raw(&self)->u32{
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _accum $lane_id _add>].read().bits()
|
||||
}
|
||||
}
|
||||
)+
|
||||
#[doc = "Interpolator " $interp]
|
||||
pub struct $interp {
|
||||
$(
|
||||
[<$lane:lower>]: [<$interp $lane>],
|
||||
)+
|
||||
}
|
||||
impl $interp{
|
||||
$(
|
||||
/// Lane accessor function
|
||||
pub fn [<get_ $lane:lower>](&mut self)->&mut [<$interp $lane>]{
|
||||
&mut self.[<$lane:lower>]
|
||||
}
|
||||
)+
|
||||
}
|
||||
impl Interp for $interp{
|
||||
fn pop(&mut self) ->u32{
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _pop_full>].read().bits()
|
||||
}
|
||||
fn peek(&self) ->u32{
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _peek_full>].read().bits()
|
||||
}
|
||||
fn set_base(&mut self, v:u32){
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _base2>].write(|w| unsafe { w.bits(v)});
|
||||
}
|
||||
fn get_base(&self)->u32{
|
||||
let sio = unsafe { &*pac::SIO::ptr() };
|
||||
sio.[<$interp:lower _base2>].read().bits()
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
)+
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
interpolators!(
|
||||
Interp0 : ([Lane0,0],[Lane1,1]),
|
||||
Interp1 : ([Lane0,0],[Lane1,1])
|
||||
);
|
||||
|
|
|
|||
Loading…
Reference in a new issue