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https://github.com/italicsjenga/rp-hal-boards.git
synced 2025-01-11 21:11:31 +11:00
Move checks in new() so initialize() cannot fail.
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parent
eb4ebc782a
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5620bdbd07
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@ -18,7 +18,12 @@ use nb::Error::WouldBlock;
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pub trait State {}
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pub trait State {}
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/// PLL is disabled.
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/// PLL is disabled.
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pub struct Disabled;
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pub struct Disabled {
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refdiv: u8,
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fbdiv: u16,
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post_div1: u8,
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post_div2: u8,
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}
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/// PLL is configured, started and locking into its designated frequency.
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/// PLL is configured, started and locking into its designated frequency.
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pub struct Locking {
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pub struct Locking {
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@ -118,19 +123,11 @@ pub mod common_configs {
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impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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/// Instantiates a new Phase-Locked-Loop device.
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/// Instantiates a new Phase-Locked-Loop device.
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pub fn new(dev: D) -> PhaseLockedLoop<Disabled, D> {
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pub fn new<R: Rate>(
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PhaseLockedLoop {
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dev: D,
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state: Disabled,
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device: dev,
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}
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}
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/// Configures and starts the PLL : it switches to Locking state.
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pub fn initialize<R: Rate>(
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self,
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xosc_frequency: Generic<u32>,
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xosc_frequency: Generic<u32>,
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config: PLLConfig<R>,
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config: PLLConfig<R>,
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) -> Result<PhaseLockedLoop<Locking, D>, Error>
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) -> Result<PhaseLockedLoop<Disabled, D>, Error>
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where
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where
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R: Into<Hertz<u64>>,
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R: Into<Hertz<u64>>,
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{
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{
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@ -155,10 +152,6 @@ impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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let ref_freq_range: Range<Hertz<u32>> = Hertz(5_000_000)..vco_freq.div(16);
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let ref_freq_range: Range<Hertz<u32>> = Hertz(5_000_000)..vco_freq.div(16);
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// Turn off PLL in case it is already running
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self.device.pwr.reset();
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self.device.fbdiv_int.reset();
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let ref_freq_hz = Hertz::<u32>::try_from(xosc_frequency)
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let ref_freq_hz = Hertz::<u32>::try_from(xosc_frequency)
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.map_err(|_| Error::BadArgument)?
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.map_err(|_| Error::BadArgument)?
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.checked_div(&(config.refdiv as u32))
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.checked_div(&(config.refdiv as u32))
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@ -168,11 +161,6 @@ impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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return Err(Error::RefFreqOutOfRange);
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return Err(Error::RefFreqOutOfRange);
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}
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}
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self.device.cs.write(|w| unsafe {
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w.refdiv().bits(config.refdiv);
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w
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});
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let fbdiv = vco_freq
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let fbdiv = vco_freq
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.checked_div(ref_freq_hz.integer())
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.checked_div(ref_freq_hz.integer())
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.ok_or(Error::BadArgument)?;
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.ok_or(Error::BadArgument)?;
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@ -185,8 +173,34 @@ impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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return Err(Error::FBDIVOutOfRange);
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return Err(Error::FBDIVOutOfRange);
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}
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}
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let refdiv = config.refdiv;
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let post_div1 = config.post_div1;
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let post_div2 = config.post_div2;
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Ok(PhaseLockedLoop {
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state: Disabled {
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refdiv,
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fbdiv,
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post_div1,
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post_div2,
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},
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device: dev,
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})
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}
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/// Configures and starts the PLL : it switches to Locking state.
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pub fn initialize(self) -> PhaseLockedLoop<Locking, D> {
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// Turn off PLL in case it is already running
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self.device.pwr.reset();
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self.device.fbdiv_int.reset();
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self.device.cs.write(|w| unsafe {
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w.refdiv().bits(self.state.refdiv);
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w
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});
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self.device.fbdiv_int.write(|w| unsafe {
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self.device.fbdiv_int.write(|w| unsafe {
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w.fbdiv_int().bits(fbdiv);
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w.fbdiv_int().bits(self.state.fbdiv);
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w
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w
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});
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});
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@ -197,13 +211,13 @@ impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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w
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w
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});
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});
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let post_div1 = config.post_div1;
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let post_div1 = self.state.post_div1;
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let post_div2 = config.post_div2;
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let post_div2 = self.state.post_div2;
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Ok(self.transition(Locking {
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self.transition(Locking {
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post_div1,
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post_div1,
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post_div2,
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post_div2,
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}))
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})
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}
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}
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}
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}
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