From 57e99438360ff3df85d0569d0515dff250fb2f43 Mon Sep 17 00:00:00 2001
From: 9names <60134748+9names@users.noreply.github.com>
Date: Thu, 20 Jan 2022 21:55:16 +1100
Subject: [PATCH] Set hw reset bits for watchdog

---
 rp2040-hal/src/watchdog.rs | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/rp2040-hal/src/watchdog.rs b/rp2040-hal/src/watchdog.rs
index a355268..21d3725 100644
--- a/rp2040-hal/src/watchdog.rs
+++ b/rp2040-hal/src/watchdog.rs
@@ -92,6 +92,21 @@ impl Watchdog {
     fn enable(&self, bit: bool) {
         self.watchdog.ctrl.write(|w| w.enable().bit(bit))
     }
+
+    /// Configure which hardware will be reset by the watchdog
+    /// the default is everything except ROSC, XOSC
+    ///
+    /// Safety: ensure no other device is writing to psm.wdsel
+    /// This is easy at the moment, since nothing else uses PSM
+    unsafe fn configure_wdog_reset_triggers(&self) {
+        let psm = &*pac::PSM::ptr();
+        psm.wdsel.write_with_zero(|w| {
+            w.bits(0x0001ffff);
+            w.xosc().clear_bit();
+            w.rosc().clear_bit();
+            w
+        });
+    }
 }
 
 impl watchdog::Watchdog for Watchdog {
@@ -124,6 +139,9 @@ impl watchdog::WatchdogEnable for Watchdog {
         }
 
         self.enable(false);
+        unsafe {
+            self.configure_wdog_reset_triggers();
+        }
         self.load_counter(self.delay_ms);
         self.enable(true);
     }