From 596bea309b89e5104c512ff93474d41a5f8219ee Mon Sep 17 00:00:00 2001
From: jspaulsen <jpaulsen@lo3energy.com>
Date: Sat, 15 May 2021 10:32:14 -0700
Subject: [PATCH] Initial watchdog implementation

---
 rp2040-hal/src/watchdog.rs | 74 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 73 insertions(+), 1 deletion(-)

diff --git a/rp2040-hal/src/watchdog.rs b/rp2040-hal/src/watchdog.rs
index 31c93dc..2006af0 100644
--- a/rp2040-hal/src/watchdog.rs
+++ b/rp2040-hal/src/watchdog.rs
@@ -1,3 +1,75 @@
 //! Watchdog
 // See [Chapter 4 Section 7](https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf) for more details
-// TODO
+use embedded_hal::watchdog;
+use embedded_time::{
+    duration,
+    fixed_point::FixedPoint,
+};
+use crate::pac::WATCHDOG;
+
+
+//const MAX_LOAD: u32 = 0x7FFFFF;
+
+
+pub struct Watchdog {
+    watchdog: WATCHDOG,
+    delay_ms: u32,
+}
+
+impl Watchdog {
+    pub fn new(watchdog: WATCHDOG) -> Self {
+        Self {
+            watchdog,
+            delay_ms: 0,
+        }
+    }
+
+    pub fn enable_tick_generation(&mut self, cycles: u8) {
+        const WATCHDOG_TICK_ENABLE_BITS: u32 = 0x200;
+
+        self.watchdog
+            .tick
+            .write(|w| unsafe { w.bits(WATCHDOG_TICK_ENABLE_BITS | cycles as u32)})
+    }
+
+    fn load_counter(&self, counter: u32) {
+        self.watchdog
+            .load
+            .write(|w| unsafe { w.bits(counter)});
+    }
+
+    fn enable(&self) {
+        self.watchdog
+            .ctrl
+            .write(|w| w.enable().set_bit())
+    }
+}
+
+impl watchdog::Watchdog for Watchdog {
+    fn feed(&mut self) {
+        self.load_counter(self.delay_ms)
+    }
+}
+
+impl watchdog::WatchdogEnable for Watchdog {
+    type Time = duration::Microseconds;
+
+    /// Due to a logic error, the watchdog decrements by 2 and
+    /// value must be compensated; see RP2040-E1
+    fn start<T: Into<Self::Time>>(&mut self, period: T) {
+        let delay_ms = period
+            .into()
+            .integer() * 2;
+
+        self.load_counter(delay_ms);
+        self.enable();
+    }
+}
+
+impl watchdog::WatchdogDisable for Watchdog {
+    fn disable(&mut self) {
+        self.watchdog
+            .ctrl
+            .write(|w| w.enable().clear_bit())
+    }
+}