mirror of
https://github.com/italicsjenga/rp-hal-boards.git
synced 2024-12-24 05:01:31 +11:00
Hmvp
GitHub
parent
c4f30a8ba6
commit
614180eda3
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@ -7,6 +7,10 @@ macro_rules! int_division {
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w
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});
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}
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fn get_int_div(&self) -> usize {
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unsafe { self.shared_dev.get() }.$div.read().int().bits() as usize
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}
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}
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};
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}
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@ -20,6 +24,32 @@ macro_rules! frac_division {
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w
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});
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}
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fn get_frac_div(&self) -> usize {
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unsafe { self.shared_dev.get() }
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.$div
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.read()
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.frac()
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.bits()
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.into()
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}
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}
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};
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}
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macro_rules! division {
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($name:ident, $div:ident) => {
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impl ClockDivision for $name {
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fn set_div(&mut self, div: u32) {
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unsafe { self.shared_dev.get() }.$div.modify(|_, w| unsafe {
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w.bits(div);
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w
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});
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}
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fn get_div(&self) -> u32 {
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unsafe { self.shared_dev.get() }.$div.read().bits()
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}
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}
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};
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}
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@ -1,11 +1,40 @@
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//! Clocks (CLOCKS)
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// See [Chapter 2 Section 15](https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf) for more details
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//!
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//!
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//!
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//! Usage:
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//! ```rust
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//! let mut p = rp2040_pac::Peripherals::take().unwrap();
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//! let mut watchdog = Watchdog::new(p.WATCHDOG);
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//! let mut clocks = ClocksManager::new(p.CLOCKS, &mut watchdog);
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//! // Enable the xosc
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//! let xosc = setup_xosc_blocking(p.XOSC, XOSC_MHZ.Hz()).ok().unwrap();
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//!
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//!
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//! // Configure PLLs
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//! // REF FBDIV VCO POSTDIV
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//! // PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
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//! // PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz
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//! let pll_sys =
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//! setup_pll_blocking(p.PLL_SYS, 12.MHz().into(), PLL_SYS_125MHZ, &mut clocks, &mut p.RESETS).ok().unwrap();
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//! let pll_usb =
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//! setup_pll_blocking(p.PLL_USB, 12.MHz().into(), PLL_USB_48MHZ, &mut clocks, &mut p.RESETS).ok().unwrap();
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//! clocks.init(&xosc, &pll_sys, &pll_usb);
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//! ```
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//!
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//! See [Chapter 2 Section 15](https://datasheets.raspberrypi.org/rp2040/rp2040_datasheet.pdf) for more details
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use crate::pac::*;
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use crate::{
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pll::{Locked, PhaseLockedLoop},
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watchdog::Watchdog,
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xosc::{CrystalOscillator, Stable},
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};
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use core::convert::TryInto;
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use embedded_time::rate::*;
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use pac::{clocks, CLOCKS, PLL_SYS, PLL_USB};
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#[macro_use]
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mod macros;
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#[derive(Copy, Clone)]
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/// Provides refs to the CLOCKS block.
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pub struct ShareableClocks {
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@ -22,6 +51,17 @@ impl ShareableClocks {
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}
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}
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const XOSC_MHZ: u32 = 12_000_000_u32;
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fn make_div<S: TryInto<Hertz<u64>>, F: TryInto<Hertz<u64>>>(
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src_freq: S,
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freq: F,
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) -> Result<u32, ()> {
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let src_freq = *src_freq.try_into().map_err(|_| ())?.integer();
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let freq = *freq.try_into().map_err(|_| ())?.integer();
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let div: u64 = (src_freq << 8).wrapping_div(freq);
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Ok(div as u32)
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}
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/// Abstraction layer providing Clock Management.
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pub struct ClocksManager {
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clocks: CLOCKS,
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@ -29,7 +69,13 @@ pub struct ClocksManager {
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}
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impl ClocksManager {
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/// Exchanges CLOCKS block against Self.
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pub fn new(mut clocks_block: CLOCKS) -> Self {
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pub fn new(mut clocks_block: CLOCKS, watchdog: &mut Watchdog) -> Self {
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// Start tick in watchdog
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watchdog.enable_tick_generation(XOSC_MHZ as u8);
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// Disable resus that may be enabled from previous software
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clocks_block.clk_sys_resus_ctrl.write_with_zero(|w| w);
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let shared_clocks = ShareableClocks::new(&mut clocks_block);
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ClocksManager {
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clocks: clocks_block,
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@ -37,6 +83,81 @@ impl ClocksManager {
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}
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}
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/// Initialize the clocks
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pub fn init(
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&self,
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_: &CrystalOscillator<Stable>,
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_: &PhaseLockedLoop<Locked, PLL_SYS>,
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_: &PhaseLockedLoop<Locked, PLL_USB>,
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) {
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// Configure clocks
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// CLK_REF = XOSC (12MHz) / 1 = 12MHz
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let mut ref_clock = self.ref_clock();
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let div = make_div(12u32.MHz(), 12u32.MHz()).unwrap();
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// If increasing divisor, set divisor before source.
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if div > ref_clock.get_div() {
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ref_clock.set_div(div);
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}
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ref_clock.set_xosc_src();
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ref_clock.await_select(2);
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ref_clock.set_div(div);
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// CLK SYS = PLL SYS (125MHz) / 1 = 125MHz
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let mut sys_clock = self.sys_clock();
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let div = make_div(125u32.MHz(), 125u32.MHz()).unwrap();
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// If increasing divisor, set divisor before source.
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if div > sys_clock.get_div() {
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sys_clock.set_div(div);
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}
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sys_clock.set_pll_sys_auxsrc();
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sys_clock.set_self_aux_src();
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sys_clock.await_select(1);
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sys_clock.set_div(div);
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// CLK USB = PLL USB (48MHz) / 1 = 48MHz
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let mut usb_clock = self.usb_clock();
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let div = make_div(48u32.MHz(), 48u32.MHz()).unwrap();
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// If increasing divisor, set divisor before source.
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if div > usb_clock.get_div() {
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usb_clock.set_div(div);
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}
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usb_clock.disable();
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usb_clock.set_pll_usb_auxsrc();
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usb_clock.enable();
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usb_clock.set_div(div);
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// CLK ADC = PLL USB (48MHZ) / 1 = 48MHz
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let mut adc_clock = self.adc_clock();
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let div = make_div(48u32.MHz(), 48u32.MHz()).unwrap();
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// If increasing divisor, set divisor before source.
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if div > adc_clock.get_div() {
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adc_clock.set_div(div);
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}
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adc_clock.disable();
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adc_clock.set_pll_usb_auxsrc();
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adc_clock.enable();
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adc_clock.set_div(div);
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// CLK RTC = PLL USB (48MHz) / 1024 = 46875Hz
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let mut rtc_clock = self.rtc_clock();
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let div = make_div(48u32.MHz(), 46875u32.Hz()).unwrap();
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// If increasing divisor, set divisor before source.
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if div > rtc_clock.get_div() {
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rtc_clock.set_div(div);
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}
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rtc_clock.disable();
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rtc_clock.set_pll_usb_auxsrc();
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rtc_clock.enable();
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rtc_clock.set_div(div);
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// CLK PERI = clk_sys. Used as reference clock for Peripherals. No dividers so just select and enable
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// Normally choose clk_sys or clk_usb
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let mut peripheral_clock = self.peripheral_clock();
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peripheral_clock.disable();
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peripheral_clock.set_clksys_auxsrc();
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peripheral_clock.enable();
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}
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/// Releases the CLOCKS block
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pub fn free(self) -> CLOCKS {
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self.clocks
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@ -117,12 +238,24 @@ impl ClocksManager {
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pub trait IntegerDivision {
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/// Set integer divider value.
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fn set_int_div(&mut self, div: usize);
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/// Get integer diveder value.
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fn get_int_div(&self) -> usize;
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}
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/// For clocks with a fraction divider.
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pub trait FractionDivision {
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/// Set fraction divider value.
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fn set_frac_div(&mut self, div: usize);
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/// Get fraction divider value.
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fn get_frac_div(&self) -> usize;
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}
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/// For clocks with a divider
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pub trait ClockDivision {
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/// Set integer divider value.
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fn set_div(&mut self, div: u32);
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/// Get integer diveder value.
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fn get_div(&self) -> u32;
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}
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/// For clocks that can have XOSC as source.
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@ -242,6 +375,7 @@ clockadc_auxsource!(GpioOutput0Clock, clk_gpout0_ctrl);
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clockrtc_auxsource!(GpioOutput0Clock, clk_gpout0_ctrl);
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clockref_auxsource!(GpioOutput0Clock, clk_gpout0_ctrl);
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division!(GpioOutput0Clock, clk_gpout0_div);
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int_division!(GpioOutput0Clock, clk_gpout0_div, u32);
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frac_division!(GpioOutput0Clock, clk_gpout0_div, u8);
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@ -265,6 +399,7 @@ clockadc_auxsource!(GpioOutput1Clock, clk_gpout1_ctrl);
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clockrtc_auxsource!(GpioOutput1Clock, clk_gpout1_ctrl);
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clockref_auxsource!(GpioOutput1Clock, clk_gpout1_ctrl);
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division!(GpioOutput1Clock, clk_gpout1_div);
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int_division!(GpioOutput1Clock, clk_gpout1_div, u32);
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frac_division!(GpioOutput1Clock, clk_gpout1_div, u8);
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@ -288,6 +423,7 @@ clockadc_auxsource!(GpioOutput2Clock, clk_gpout2_ctrl);
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clockrtc_auxsource!(GpioOutput2Clock, clk_gpout2_ctrl);
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clockref_auxsource!(GpioOutput2Clock, clk_gpout2_ctrl);
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division!(GpioOutput2Clock, clk_gpout2_div);
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int_division!(GpioOutput2Clock, clk_gpout2_div, u32);
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frac_division!(GpioOutput2Clock, clk_gpout2_div, u8);
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@ -311,6 +447,7 @@ clockadc_auxsource!(GpioOutput3Clock, clk_gpout3_ctrl);
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clockrtc_auxsource!(GpioOutput3Clock, clk_gpout3_ctrl);
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clockref_auxsource!(GpioOutput3Clock, clk_gpout3_ctrl);
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division!(GpioOutput3Clock, clk_gpout3_div);
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int_division!(GpioOutput3Clock, clk_gpout3_div, u32);
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frac_division!(GpioOutput3Clock, clk_gpout3_div, u8);
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@ -318,6 +455,30 @@ frac_division!(GpioOutput3Clock, clk_gpout3_div, u8);
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pub struct ReferenceClock {
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shared_dev: ShareableClocks,
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}
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impl ReferenceClock {
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/// WIP - Helper function to reset source (blocking)
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pub fn reset_source_await(&mut self) {
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let shared_dev = unsafe { self.shared_dev.get() };
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shared_dev.clk_ref_ctrl.write(|w| {
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unsafe { w.src().bits(0) };
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w
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});
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self.await_select(0x0);
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}
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/// WIP - Helper function to select new source (blocking)
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pub fn await_select(&self, clock: u8) {
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let shared_dev = unsafe { self.shared_dev.get() };
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while (shared_dev.clk_ref_selected.read().bits() & (1 << clock)) == 0 {
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cortex_m::asm::nop();
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}
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}
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}
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rosc_source!(ReferenceClock, clk_ref_ctrl);
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selfaux_source!(ReferenceClock, clk_ref_ctrl, clksrc_clk_ref_aux);
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xosc_source!(ReferenceClock, clk_ref_ctrl);
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@ -327,15 +488,14 @@ pll_usb_auxsource!(ReferenceClock, clk_ref_ctrl);
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gpin0_auxsource!(ReferenceClock, clk_ref_ctrl);
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gpin1_auxsource!(ReferenceClock, clk_ref_ctrl);
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int_division!(ReferenceClock, clk_ref_div, u8);
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division!(ReferenceClock, clk_ref_div);
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/// System Clock
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pub struct SystemClock {
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shared_dev: ShareableClocks,
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}
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impl SystemClock {
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/// WIP - Helper function to reset source (blocking)
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pub fn reset_source_await(&self) {
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pub fn reset_source_await(&mut self) {
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let shared_dev = unsafe { self.shared_dev.get() };
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shared_dev.clk_sys_ctrl.write(|w| {
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@ -343,14 +503,14 @@ impl SystemClock {
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w
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});
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self.await_select(0x1);
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self.await_select(0x0);
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}
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/// WIP - Helper function to select new source (blocking)
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pub fn await_select(&self, clock: u8) {
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let shared_dev = unsafe { self.shared_dev.get() };
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while shared_dev.clk_sys_selected.read().bits() != clock as u32 {
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while (shared_dev.clk_sys_selected.read().bits() & (1 << clock)) == 0 {
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cortex_m::asm::nop();
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}
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}
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@ -368,6 +528,7 @@ xosc_auxsource!(SystemClock, clk_sys_ctrl);
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gpin0_auxsource!(SystemClock, clk_sys_ctrl);
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gpin1_auxsource!(SystemClock, clk_sys_ctrl);
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division!(SystemClock, clk_sys_div);
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int_division!(SystemClock, clk_sys_div, u32);
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frac_division!(SystemClock, clk_sys_div, u8);
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@ -400,7 +561,7 @@ xosc_auxsource!(UsbClock, clk_usb_ctrl);
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gpin0_auxsource!(UsbClock, clk_usb_ctrl);
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gpin1_auxsource!(UsbClock, clk_usb_ctrl);
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int_division!(UsbClock, clk_usb_div, u8);
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division!(UsbClock, clk_usb_div);
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/// Adc Clock
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pub struct AdcClock {
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@ -416,7 +577,7 @@ xosc_auxsource!(AdcClock, clk_adc_ctrl);
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gpin0_auxsource!(AdcClock, clk_adc_ctrl);
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gpin1_auxsource!(AdcClock, clk_adc_ctrl);
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int_division!(AdcClock, clk_adc_div, u8);
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division!(AdcClock, clk_adc_div);
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/// RTC Clock
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pub struct RtcClock {
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@ -432,5 +593,6 @@ xosc_auxsource!(RtcClock, clk_rtc_ctrl);
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gpin0_auxsource!(RtcClock, clk_rtc_ctrl);
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gpin1_auxsource!(RtcClock, clk_rtc_ctrl);
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division!(RtcClock, clk_rtc_div);
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int_division!(RtcClock, clk_rtc_div, u32);
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frac_division!(RtcClock, clk_rtc_div, u8);
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@ -13,8 +13,9 @@ use embedded_time::{
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};
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use nb::Error::WouldBlock;
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use pac::RESETS;
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use crate::resets::SubsystemReset;
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use crate::{clocks::ClocksManager, resets::SubsystemReset};
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/// State of the PLL
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pub trait State {}
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@ -264,3 +265,28 @@ impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Locking, D> {
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self.transition(Locked)
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}
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}
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/// Blocking helper method to setup the PLL without going through all the steps.
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pub fn setup_pll_blocking<D: PhaseLockedLoopDevice, R: Rate>(
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dev: D,
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xosc_frequency: Generic<u32>,
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config: PLLConfig<R>,
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clocks: &mut ClocksManager,
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resets: &mut RESETS,
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) -> Result<PhaseLockedLoop<Locked, D>, Error>
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where
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R: Into<Hertz<u64>>,
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{
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// Before we touch PLLs, switch sys and ref cleanly away from their aux sources.
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let mut sys_clock = clocks.sys_clock();
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sys_clock.reset_source_await();
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let mut ref_clock = clocks.ref_clock();
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ref_clock.reset_source_await();
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let initialized_pll = PhaseLockedLoop::new(dev, xosc_frequency, config)?.initialize(resets);
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let locked_pll_token = nb::block!(initialized_pll.await_lock()).unwrap();
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Ok(initialized_pll.get_locked(locked_pll_token))
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}
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