mirror of
https://github.com/italicsjenga/rp-hal-boards.git
synced 2024-12-24 05:01:31 +11:00
Move PLL parameters into a struct to help testability and reconfiguration of the PLL.
This commit is contained in:
parent
9be7c41400
commit
649998189f
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@ -4,7 +4,8 @@
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use core::{
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use core::{
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convert::{
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convert::{
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Infallible,
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Infallible,
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TryFrom
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TryFrom,
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TryInto
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},
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},
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marker::PhantomData,
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marker::PhantomData,
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ops::{
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ops::{
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@ -18,7 +19,8 @@ use embedded_time::{
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fixed_point::FixedPoint,
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fixed_point::FixedPoint,
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rate::{
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rate::{
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Hertz,
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Hertz,
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Generic
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Generic,
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Rate
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}
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}
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};
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};
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@ -28,10 +30,11 @@ use nb::Error::WouldBlock;
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pub trait State {}
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pub trait State {}
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/// PLL is disabled but is configured.
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/// PLL is disabled.
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pub struct Disabled {
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pub struct Disabled;
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refdiv: u8,
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vco_freq: Hertz,
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/// PLL is configured, started and locking into its designated frequency.
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pub struct Locking {
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post_div1: u8,
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post_div1: u8,
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post_div2: u8
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post_div2: u8
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}
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}
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@ -39,17 +42,10 @@ pub struct Disabled {
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/// PLL is locked : it delivers a steady frequency.
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/// PLL is locked : it delivers a steady frequency.
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pub struct Locked;
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pub struct Locked;
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/// PLL is locking into its designated frequency.
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pub struct Locking {
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post_div1: u8,
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post_div2: u8
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}
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impl State for Disabled {}
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impl State for Disabled {}
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impl State for Locked {}
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impl State for Locked {}
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impl State for Locking {}
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impl State for Locking {}
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/// Trait to handle both underlying devices from the PAC (PLL_SYS & PLL_USB)
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/// Trait to handle both underlying devices from the PAC (PLL_SYS & PLL_USB)
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pub trait PhaseLockedLoopDevice: Deref<Target = rp2040_pac::pll_sys::RegisterBlock> {}
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pub trait PhaseLockedLoopDevice: Deref<Target = rp2040_pac::pll_sys::RegisterBlock> {}
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@ -97,49 +93,83 @@ pub enum Error {
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BadArgument
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BadArgument
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}
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}
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/// Parameters for a PLL.
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pub struct PLLConfig<R: Rate> {
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/// Voltage Controlled Oscillator frequency.
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pub vco_freq: R,
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/// Reference divider
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pub refdiv: u8,
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/// Post Divider 1
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pub post_div1: u8,
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/// Post Divider 2
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pub post_div2: u8
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}
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/// Common configs for the two PLLs. Both assume the XOSC is cadenced at 12MHz !
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/// See Chapter 2, Section 18, §2
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pub mod common_configs {
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use super::PLLConfig;
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use embedded_time::rate::Megahertz;
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/// Default, nominal configuration for PLL_SYS
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pub const PLL_SYS_125MHZ: PLLConfig<Megahertz> = PLLConfig {
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vco_freq: Megahertz(1500),
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refdiv: 1,
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post_div1: 6,
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post_div2: 2
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};
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/// Default, nominal configuration for PLL_USB.
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pub const PLL_USB_48MHZ: PLLConfig<Megahertz> = PLLConfig {
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vco_freq: Megahertz(480),
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refdiv: 1,
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post_div1: 5,
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post_div2: 2
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};
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}
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impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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/// Instantiates a new Phase-Locked-Loop device.
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pub fn new(dev: D) -> PhaseLockedLoop<Disabled, D> {
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PhaseLockedLoop {
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state: Disabled,
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device: dev,
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}
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}
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/// Instantiates and configures a new Phase-Locked-Loop device.
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/// Configures and starts the PLL : it switches to Locking state.
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pub fn new(dev: D, refdiv: u8, vco_freq: Generic<u32>, post_div1: u8, post_div2: u8) -> Result<PhaseLockedLoop<Disabled, D>, Error> {
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pub fn initialize<R: Rate>(self, xosc_frequency: Generic<u32>, config: PLLConfig<R>) -> Result<PhaseLockedLoop<Locking, D>, Error> where R: Into<Hertz> {
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const VCO_FREQ_RANGE: RangeInclusive<Hertz<u32>> = Hertz(400_000_000)..=Hertz(1600_000_000);
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const VCO_FREQ_RANGE: RangeInclusive<Hertz<u32>> = Hertz(400_000_000)..=Hertz(1600_000_000);
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const POSTDIV_RANGE: Range<u8> = 1..7;
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const POSTDIV_RANGE: Range<u8> = 1..7;
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const FBDIV_RANGE: Range<u16> = 16..320;
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let vco_freq = Hertz::<u32>::try_from(vco_freq).map_err(|_| Error::BadArgument)?;
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let vco_freq: Hertz = config.vco_freq.try_into().map_err(|_| Error::BadArgument)?;
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if !VCO_FREQ_RANGE.contains(&vco_freq) {
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if !VCO_FREQ_RANGE.contains(&vco_freq) {
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return Err(Error::VCOFreqOutOfRange)
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return Err(Error::VCOFreqOutOfRange)
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}
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}
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if !POSTDIV_RANGE.contains(&post_div1) || !POSTDIV_RANGE.contains(&post_div2) {
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if !POSTDIV_RANGE.contains(&config.post_div2) || !POSTDIV_RANGE.contains(&config.post_div2) {
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return Err(Error::PostDivOutOfRage)
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return Err(Error::PostDivOutOfRage)
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}
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}
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Ok(PhaseLockedLoop {
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let ref_freq_range: Range<Hertz<u32>> = Hertz(5_000_000)..vco_freq.div(16);
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state: Disabled {
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refdiv, vco_freq, post_div1, post_div2
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},
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device: dev,
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})
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}
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/// Configures and starts the PLL : it switches to Locking state.
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pub fn initialize(self, xosc_frequency: Generic<u32>) -> Result<PhaseLockedLoop<Locking, D>, Error>{
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const FBDIV_RANGE: Range<u16> = 16..320;
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let ref_freq_range: Range<Hertz<u32>> = Hertz(5_000_000)..self.state.vco_freq.div(16);
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// Turn off PLL in case it is already running
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// Turn off PLL in case it is already running
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self.device.pwr.reset();
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self.device.pwr.reset();
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self.device.fbdiv_int.reset();
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self.device.fbdiv_int.reset();
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let refdiv = self.state.refdiv;
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let ref_freq_hz = Hertz::<u32>::try_from(xosc_frequency).
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let ref_freq_hz = Hertz::<u32>::try_from(xosc_frequency).
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map_err(|_| Error::BadArgument)?.
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map_err(|_| Error::BadArgument)?.
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checked_div(&(refdiv as u32)).
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checked_div(&(config.refdiv as u32)).
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ok_or(Error::BadArgument)?;
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ok_or(Error::BadArgument)?;
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if !ref_freq_range.contains(&ref_freq_hz) {
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if !ref_freq_range.contains(&ref_freq_hz) {
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@ -147,12 +177,14 @@ impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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}
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}
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self.device.cs.write(|w| unsafe {
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self.device.cs.write(|w| unsafe {
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w.refdiv().bits(refdiv as u8);
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w.refdiv().bits(config.refdiv);
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w
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w
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});
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});
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let fbdiv = *self.state.vco_freq.checked_div(ref_freq_hz.integer()).
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let fbdiv = vco_freq.checked_div(ref_freq_hz.integer()).
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ok_or(Error::BadArgument)?.integer() as u16;
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ok_or(Error::BadArgument)?;
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let fbdiv: u16 = (*fbdiv.integer()).try_into().map_err(|_| Error::BadArgument)?;
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if !FBDIV_RANGE.contains(&fbdiv) {
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if !FBDIV_RANGE.contains(&fbdiv) {
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return Err(Error::FBDIVOutOfRange)
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return Err(Error::FBDIVOutOfRange)
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@ -163,11 +195,6 @@ impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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w
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w
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});
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});
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self.device.cs.write(|w| unsafe {
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w.refdiv().bits(refdiv);
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w
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});
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// Turn on self.device
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// Turn on self.device
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self.device.pwr.write(|w| unsafe {
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self.device.pwr.write(|w| unsafe {
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//w.pd().clear_bit();
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//w.pd().clear_bit();
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@ -176,8 +203,8 @@ impl<D: PhaseLockedLoopDevice> PhaseLockedLoop<Disabled, D> {
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w
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w
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});
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});
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let post_div1 = self.state.post_div1;
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let post_div1 = config.post_div1;
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let post_div2 = self.state.post_div2;
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let post_div2 = config.post_div2;
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Ok(self.transition(Locking {
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Ok(self.transition(Locking {
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post_div1, post_div2
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post_div1, post_div2
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